chris_li
Member level 2
If I have a hierarchy design on hands with brief information as below
* top-level has three subblocks(A, B and C)
* only one main clock, period is 2500ps
* data path: primary input->A->B->C->primary output
After each subblock PnR independently, each of them has around 1000ps clock_insertion_delay, next how to do top-level CTS? Any point need to pay more attentions?
* top-level has three subblocks(A, B and C)
* only one main clock, period is 2500ps
* data path: primary input->A->B->C->primary output
After each subblock PnR independently, each of them has around 1000ps clock_insertion_delay, next how to do top-level CTS? Any point need to pay more attentions?
