Trouble getting started with a Spartan-6

I guess more specifically, for the following declarations of datain

NET "datain_p[0]" DIFF_TERM = "TRUE";
NET "datain_p[0]" IOSTANDARD = LVDS_33;
NET "datain_p[0]" LOC = R3;
NET "datain_n[0]" DIFF_TERM = "TRUE";
NET "datain_n[0]" IOSTANDARD = LVDS_33;
NET "datain_n[0]" LOC = T3;
NET "datain_p[1]" DIFF_TERM = "TRUE";
NET "datain_p[1]" IOSTANDARD = LVDS_33;
NET "datain_p[1]" LOC = T4;
NET "datain_n[1]" DIFF_TERM = "TRUE";
NET "datain_n[1]" IOSTANDARD = LVDS_33;
NET "datain_n[1]" LOC = V4;

What inputs are valid for clkin_p and clkin_n? I've tried a bunch of "clock" eligible pins and it seems to always complain that they are not on the same half-bank. When I don't declare where clkin should be in the ucf it place and routes just fine.

This is detailed in UG385 - Spartan-6 FPGA Packaging and Pinouts, Tables 2-*, "BUFIO2 region".

If you don't constrain the pin, the tools will pick a suitable pin for you, which only helps if you haven't already got a finished board in front of you.

If your clock spans a half bank, you have a couple of options - drive clock pins on each half bank using the same clock source (possibly buffered), or if your clock rate isn't too high, use a BUFG arrangement with two BUFIO2s per half bank, à la clock_generator_DDR_s8_diff.v.

Whats considered too fast for using the BUFG arrangement with two BUFIO2s per half bank? I'm pretty constrained here using this Drigmorn3 board.

EnderW4785 said:

Whats considered too fast for using the BUFG arrangement with two BUFIO2s per half bank? I'm pretty constrained here using this Drigmorn3 board.

Click to expand...

Not sure - it works just fine for me at 50 MHz though. The Fmax for BUFG is 375 to 400 MHz depending on the speed grade, but you will probably be limited by other things (signal integrity being the most obvious) before you get anywhere near that.

You can always see if it's possible to achieve timing closure before doing anything else.

That makes sense and I think I can make due with that for a proof-of-concept. Although I'm clearly missing something. This code works in simulation:

//Buffer the input clock to be available for the another bank (limits clock rate to ??)
clock_generator_ddr_s8_diff #(
.S (S),
.DIFF_TERM ("FALSE"))
inst_clkgen(
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.ioclkap (ioclkap),
.ioclkan (ioclkan),
.serdesstrobea (serdesstrobea),
.gclk (gclk));

//Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_ddr_s8_diff #(
.S (S), // Set the serdes factor
.DIFF_TERM ("TRUE")) // Enable or disable diff termination
inst_clkin (
.clkin_p (ioclkap),
.clkin_n (ioclkan),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_x1 (rx_bufg_x1));

// Data Inputs
serdes_1_to_n_data_ddr_s8_diff #(
.S (S),
.D (D),
.DIFF_TERM ("TRUE")) // Enable or disable diff termination
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bslip),
.reset (rst),
.data_out (rxd),
.debug_in (2'b00),
.debug ());

But when I try to implement the design I get the error that ERROR:NgdBuild:770 - IBUFDS 'IBUFDS' and IBUFDS 'IBUFDS_0' on net 'ioclkap' are
lined up in series. Buffers of the same direction cannot be placed in series. So, the translate failed. Can someone translate this for me?

On a brighter note, we are hiring a consultant that may be able to help me with some of these issues so I won't be so helpless!