Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] ground plane noise at higher voltages

Status
Not open for further replies.
R

resonant

Newbie level 6
Joined
Sep 24, 2011
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,378
good day everyone

I'm having a problem not exactly sure what the cause is but I suspect its ground plane noise. I'm using a PIC to generate a PWM signal to my power circuit at about 60 kHz. Whenever I push the input voltage past 50 - 60 V the system doesnt switch properly. up until 50 V it works perfect. I suspect the PWM signal is getting distorted. I'm using a half bridge configuration and above 50 V the output waveform decreases and gets distorted. Please if anyone who has encountered a similar problem please help me.

Thanks
 

can u provide the schematic of ur circuit and components used in it
 

cannot at the moment will post later today. At one point the PWM pin on the PIC stopped working when I pushed the system up to 230 V

---------- Post added at 23:05 ---------- Previous post was at 23:02 ----------

could possibly be a fault with my bootstrap circuit. but i built it with the exact same components (diodes, caps etc.) and still having the same problem.

---------- Post added at 23:06 ---------- Previous post was at 23:05 ----------

To power my pic i'm using a voltage regulator which steps down from 21 V to 3.3 V

---------- Post added at 23:08 ---------- Previous post was at 23:06 ----------

for my gatedrive circuit im using a bootstrap diode with Trr = 20 ns and a 10 uF cap. I varied the cap from 68n to 10 uF with the same results

---------- Post added at 23:10 ---------- Previous post was at 23:08 ----------

One thing that might be the problem is I'm using two regulators to supply the PIC. one from 21 V to 12 V which supplies power to other components and a 12 V to 3.3 V that powers my PIC. But I dont c how this could affect anything.
 

Also I measured the upper gate signal on the oscilloscope and I'm getting a signal that has a duty ratio of about 3% three times in a cycle

---------- Post added at 02:30 ---------- Previous post was at 02:29 ----------

hence my output current waveform decreases as soon as I reach 50+ V.

---------- Post added at 02:32 ---------- Previous post was at 02:30 ----------

using the ADC to vary the pwm of the pic.

---------- Post added at 02:33 ---------- Previous post was at 02:32 ----------

If the circuit switches properly but at a certain voltage stop could it be a problem with my bootstrap circuit?
 

There are many possible explanations for this, especially since you haven't shown a schematic or layout. You need to identify if the MCU is getting confused or reset and its PWM signals are incorrect. It might be that the switching transients from the half bridge are getting into your ADC somehow and creating a bizarre feedback loop. But it definitely sounds like a layout/EMI issue. A picture of the circuit test setup would be helpful. It's also possible that there's an issue with the bootstrapping driver, but I highly doubt it has to do with the bootstrapping components.
 
going to rebuild the circuit n c
 
Last edited:

put a resistor between the input of the gate driver and ground and it seems as if it sorted out the problem
 

An error depending on switching voltage seems to indicate that there is some EMI capacitive coupling...
Try using 4.7 kOhm pulldown as close as possible to the gate driver. Sometimes a low pass (high frequency like 100 Ohm 10 pF) before the PWM input improves the performance. Take care connecting ground planes (power and controller) only in ONE SINGLE point. If false resets are happening in your controller you might use a smaller value pulldown/pullup and aditionaly a filtering capacitor. Have you checked the gate waveforms? are you expecting unwanted peaks? gate driver traces should be as short as possible.
 
I figured it out, my deadtime was set too high. I had it past the maximum set in the datasheet that why it was giving funny results at higher voltages.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top