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VHDL passing generic values from the top hierarchy to the lowest hierarchy

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shaiko

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Hello,

Is this possible to control ALL the design generics from the top hierarchy?
 

Yes, by passing the generic map from the top hierarchy to the bottom, this is possible
 
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    shaiko

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Yes, by passing it thrue the hierarchies, but not directly accessing a lower hierarchy. A similar option exists only in Verilog.
 
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FvM,

do you mean through "generic map" ?
 

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