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How to knw the fifo is full , empty, almost full, almost empty signals in asyn FIFO

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diyyadavid

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Hi Frnds,


I am using FIFO for for writing and reading the data before storing into the main memory. I generated FIFO using Xilinx Core generator.

And Instantiated in the main program.

I am unable to find the
.full
.almost full
.empty
.almost empty signals

Can anyone let me know this issue regarding how to find these signals. Thanks in Advance.
 

Hi diyyadavid,

I think you are not selected the flags (that you wants) during the FIFO generation using the Xilinx Logic Core generator. The things are there in the 3rd page of the Xilinx Logic Core generator, when you generating the FIFO... also the the read data count and the write data count are at the 5th page...
 

Yes, you must tick the flag names if you want to be available. Also I would suggest not to enable these flags if you plan not to use. You can avoid un-necessary nets...
 

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