# Help me understand the calculation of W/L ratio in analog

1. ## Need help.

Hi,
I am not understanding the calculations for W/L ratio in analog circuits. I am fabricating in 0.6um technology. Is it necessary that all the transistors lengths (L) that I use in op-amp circuit be 0.6um? If yes, then I am finding really difficult to get the current mirror going... Is it okay to have different L values for all the transistors? What might be the fabrication problems???? :(
srivatsan

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2. ## Re: Need help.

It is OK. But it is good practice to use several transistors with L=0.6u and connected in series. In this case the ratio will be more precise.

3. ## Re: Need help.

Thanks Fom.
1. Why is it better to have same length (0.6um)? Then what is the general design procedure?

2. Since differnt lenght is good for precision, why it cannot be done with single length? As such, different length can be seen with multiple transistor of same length.
srivats

4. ## Re: Need help.

During manufacturing L will be changed by DL because of etching. So real (or effective) Leff = L - DL. DL can be changed from wafer to wafer. If transistors have the same L they will have same Leff, so the ratio is not changed as well.
The same rule is for W. Try to use transistors with the same W, connected in parallel to keep the ratio precisely. If it is impossible try to keep W for different transistors as close as possible.

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5. ## Re: Need help.

Thanks for fast reply dude...
Well, when I followed the steps of designing the curretn mirror given in Razavi, and baker (2 diff books..), i am not able to find a logical way for designing them (W/L) when the resistor is fixed at 20k and this is because when i simulated using BSIM3v3.1 SPICE, the output is not (sometimes not even near) "near" to what is anticipated. :? So, how to design multiple (parallel and series) of the same transistor to get the answer? I hope I am clear.. simply put: how to design current mirror if R=20k and use L=0.6um only, for I=10 to 100uA? if you can get me across on this, I am pretty sure I will understand the analog "idea".
tahnks a lot.
srivats :)
p.s.: ia m working on it rightnow..

6. ## Need help.

Srivatsan,

Have you looked at the ratios between currents? They should be well defined (double W and you should see twice the current). Absolute values are always hard to obtain in IC technology, even in simulations they always end up where you don't expect them.

7. ## Re: Need help.

Well, when I increase the W by twice, the current shot up to 140uA when it should be 60um. I have attached the code. When you run it in on spice, change the value of W from 2.162 to 1.081um when checking the first circuit. This has been designed for 30uA generation and expected VGS is 1.2v (VGS is fixed alng with L for easy calculation).
I dont understand this at all.. pretty crazy work out there. let me know from anyone if yu can ***** this up.
srivats

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8. ## Re: Need help.

To understand the reason do the following things:
1. To eliminate possible Early effect keep the same Vds for all transistors. Change V2 value to keep node 1 voltage as much as closer to node 9 voltage. To get a very precise ratio one should use stacked mirror.
2. To twice current don't change the width of MN1. Instead insert an additional same transistor connected in parallel with MN1. The transistor width has influence upon Vth of transistor.

9. ## Re: Need help.

A transistor with 0.6u length can never be a good current mirror, as its output resistance is quite low. So if you want good mirroring, use large lengths ( ~2u) or use a cascode configuration.
There will be a lot of discrepencies with the simple square-law model and the simulated result. The best way to choose transistor sizes and overdrive voltage is by plotting the current for various combinations of width/length and using it as a reference. But anyway, for a given overdrive voltage, the ratio of widths should match the ratio of currents flowing through it, provided they are both in saturation.

10. ## Re: Need help.

Srivats..
...please remember following 2 rules for current mirrors..

1. always use Channel length which is 4-5 * Lmin ...(though this is ideal for DSM i.e < 0.25u)....the best thing wud be for u to characterize the MOS and see for which 'L' Id slope is less...use that length

2. Ensure that Vds of mirror X'tors are similar..this takes out (1+lamda* Vds) effect....also called ratio error..if any...but best is to ensure lambda is minimal...
....one more point....Use large device sizes....i see u mentioned a change of 1.08 to 2.1...this is hardly a big change....go for larger device sizes..if possible..

Regards,
@ir@ce

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