Harmonic Balance Simulation in ADS

How do I do Harmonic Balance (HB) Simulation in ADS for DROs employing parallel feedback?

I tried puting the OscTest block in the feedback loop as suggested by the documentation but I can't get any results.

I'll be good if someone can provide an example .dsn file or post a schematic.

Any info on HB sim will also be good.

Thanks!

Add the HB block.
Open HB and add the Oscport as reference. Also mark the OSC cell.
You have to add freq osc and number of harmonics.

D.J

Hi danelad,

that was what i did but i can't get anything out from the simulation.

Attached is the .dsn file for the 4GHz DRO i'm designing.

Please tell me what i did wrong.

Why do you think it hould work?
1. Your bias is not correct. If the source is short then you have to negative bias the gate.
2. The ideal transformer is loaded by 50 ohm resisors at 4 ports. at list two of them you have to take off, I'm sure the TR lones are open so you kill he oscillator if you load it by 50 ohms.
3. Did you check that the looppase is 360 deg? You might have to add a tr line.
4.you might have to add a capacitor at the source port in orderto bring thr negative resistance to the frequency.
4. In order to design such a DRO, you can open the loop or look at the Source port and be sure it has a negative resistance and a parallel resonant circuit.

D.J

Re: Harmonic Balance Simulation in @DS

Hi!

Thanks for the reply danelad. You seem to be the only in the forum who answers my posts!

I'm quite a newbie so I'll need all the help I can get.

danelad said:

1. Your bias is not correct. If the source is short then you have to negative bias the gate.

Click to expand...

The FET used is a PHEMT so biasing was correct. I checked the S-para against datasheet and they somewhat correlate.

I have since changed to a MESFET (NE76184A) due to part availability.

danelad said:

2. The ideal transformer is loaded by 50 ohm resisors at 4 ports. at list two of them you have to take off, I'm sure the TR lones are open so you kill he oscillator if you load it by 50 ohms.

Click to expand...

Yup. Mistake. I should change 2 of the endings to quarter-wavelength microstrip-line (ML) so they look like open cct?

3. Did you check that the looppase is 360 deg? You might have to add a tr line.

Click to expand...

Is there a way i can do this using ADS? How?

In S-para sim, i tried to adjust a ML between DR and drain (see fig) till i get a resonant in the S21. Is this correct?

4.you might have to add a capacitor at the source port in orderto bring thr negative resistance to the frequency.
4. In order to design such a DRO, you can open the loop or look at the Source port and be sure it has a negative resistance and a parallel resonant circuit.

Click to expand...

This is the problem I posted in another tread. Still don't know where to break the loop......


Here's my corrected schematic using a mesfet. Still no result in HB sim. Please help me.... Thanks!

Harmonic Balance Simulation in @DS

You can check the loop phase by do the open loop test. You feedback from the Drain so the feedback signal is 180 degree out of phase with the input signal. Your resonation must have the 180 degree phase shift in stead of 0. BTW if you can post the ADS project file, I would like to try.

1. The DC was not correct, now is O.K- if you look at the first schem, the Drain is positive, the S is grounded and the Gate is also positive- so you have Vgs positive and it should be negative. (For Phemt you can have a small positive but I'm sure you ment to have Idss/2 or so).
2. Generally speaking your Oscillator desugn should start from small signal. It is easierespecially for tuning etc.
3. There are several ways to design with small signal I will tell you one now:
*Add a tunable TL between the DR and the Gate.
*Make the TL between Drain to DR a tunable.
*Add an Ideal RFC between the Source and the parallel RC you have.
*Add a matched load to the Drain( you can add 50 ohms or a better choice is to match the load to a lower impedance by a parallel capacitor or any other match circuit).
* Take off the oscport.
*Now look at the Source port -( the port is directly on the Source).
Tune the TL lengths between the DR and the D and G ports till you find a negative resistance. Open Smith Chart and you might see a negative resistance in parallel to an Inductor.
* And now resonant the Sorce with the correct Capacitor value. The capacitor is loaded at the Source and it resonant the input impedance.
*The last now for today: Go back to the Ostport you have and now you will se real oscllations.

D.J

A few of my observations....

(1)Firstly your Iprobe should be in series with Rd if you want it to measure drain current, it won't measure anything where it is.

(2) for this oscillator to work you want 0/360 degrees around the loop - therefore at 4GHz the device and resonator will add electrical length - you must add more electrical length - ie microstrip line until you have 0/360 - then harmonic balance will be able to simulate.

(2) You can break the loop at the osc port an terminate both of the free ends (50 -ohms will be fine) then run a S21 simulation. phase should pass through zero at the oscillating frequency and the gain at this point must be greater than 1.

(3) The DC block across RS won't do anything, add a proper capacitor model, in any case self biasing of FET's is very hard and this type of biassing arrangement for oscillators isn't very good - better to use a negative supply and a current mirror bias circuit instead!

(4) Even though you are trying to design (at a guess) a low phase noise oscillator - hence the Dielectric resonator - if you use a FET - you will have very poor phase noise due to the high flicker corner frequency. It would be much, much better to use Bipolar transistors (you'll probably need two to get the loop gain up) instead....

hope this helps

cheers Ody

Thanks alot for the replies guys!

boy: I don't think this forum allows one to post .dsn files...

D.J:

I tried what you told me. I think I have a big problem on the DR side.
Can I find the type of loading it presents to the transistor by doing a S-parameter sim on the DR?

What are the formula for S-para of DR couipled to 2 ML?
I got the following from Galani,Waterman,Laton, "Analysis and Design of a Single-resonator GaAs FET Osc with Noise Degeneration",IEEE transaction on uWave Theory & Tech, 1984 :

S11 = (beta1-beta2-1)/(1+beta1+beta2)
S21 = S12 =2 (beta1*beta2-1)^0.5/(1+beta1+beta2)
S22 = (beta2-beta1-1)/(1+beta1+beta2)

beta1 and beta2 are the coupling factors.

And, how is beta related to turn ratio,n?
Is it n^2 = 2*Zo*beta/Q-unloaded ?

For the transistor I'm using, I need gamma at the gate and drain to be greater than 0.8 for negative resistance. Does this imply that S11 for DR must be > 0.8 ?

This the problem I discovered.... no wonder there is no osc.....
do help me out...

Oh, 1 more thing. The C at the source is for a RF gnd. If i add RFC above the RC then there'll be no RF gnd?


Lastly,

Ody:
refering to pt (2): so phase shift of DR in parallel feedback is given by phase of S21? (this is basic but i just need to confirm )
Also, are the DR s-para formula i quoted above correct?

As for (4), i agree that bipolar these days can handle the 4GHz i req with less noise. The use of MESFET here is is largely due to part limitation... if time permits for the ordering of BJTs later on, I'll try to improve on the design. BTW,which will be more efficient in terms of power consumption? The BJT DRO vs the FET DRO with the (anything but efficient) biasing i'm currently using?



Thanks guys!

dear all

i want to desing DRO working about 9.5 GHz

plz give me a links for papers or books
about DRO design

thanks

Re: Harmonic Balance Simulation in @DS

khouly said:

dear all

i want to desing DRO working about 9.5 GHz

plz give me a links for papers or books
about DRO design

thanks

Click to expand...

Hi,

Gonzalaz'z text: uWave Amp Transistor provides a good starting point. But if you want to do parallel feedback like me, do tell me when you find a good reference

yeah , i want to design parallel feedback and till now didnot find a good refference



also i need the last chapter of Stephen Mass book "microwave mixer"
the chapter is FET mixers

thanks

Hi All

for the FET I'm using in the schematic I posted, the stability circles reside on the edge of the Smith chart. Thus, there is little "unstable" region for my load and source matching.

How do I shift these circles into the Smith Chart?

I tried putting a capacitor (pico range) at the souce (above the parallel RC) but it sort of overkill, making the Load stability circle very big! Further, the Source stab circle is not shifted.

Please help! Thanks!

gecky ,

Try to follow the directions I mentioned.
For a parallel feedback you don't have to make the device instable. It is like an oscillator built from an amplifier with a parallel feedback. The amplifier is stable.

D.J

D.J. ,

I tried real hard at what you told me for the past few days but i just can't get any osc!!!

So much so i tried to design a series feedback DRO based on the example in Gonzalaz's text on pg 422. Here is my schematic:



Still no oscillation!!!!!!! Am i doing something wrong??? If need be, could you PM me your email and i send you my .dsn file?

Thanks a lot for the help!

I can't open it. Could you please print it as you did before?
A series feedback is much more simple. Just do the step I describe here:
1. Calculate the equivalent circuit of DR coupled to a TR. It is a parallel resonator and an ideal transformer to couple the resonator to the TR line. The L,C and R can be calculated with the resonane frequency and the Q.
2. Load the Source with a tunable capacitor or an open stub. Load the Drain by a low impedance circuit such as a parallel capacitor or a lamda/4 to reduce the load .
3. Look at the Gate and tune the Source cap and Drain load in order to get a "nice" negative resistance. You will find a negative resistance with series capacitor.
4. Add a 50 ohm TL to the gate, you see that the gate load is rotates around the smith chart. Tune the Gate TL till you see a negative resistance and a parallel resonance( When the S11 curve is out the smith chart and is moving from the uper side of the smith chart to the lower as a function of frequency. The frequency the curve cross the X axix is the resonance frequency.)
5. The DR is a parallel resonance and now the active circuit has a negative resistance and also a parallel resonance.
Connect the DR model and the whole circuit. Try Oscport. It must work!!!!.

D.J

Here is the schematic i attached above. It doesn't work....

Here is the stab circle of the transistor with all the feedback components.

Is it right that is design the loading at the gate to be less/equal to the pt indicated by marker M1? ie load by the DR should be < 0.717 ?

I made DR coupling so that it gives DR S11 = 0.683arg(-180). The load at the Drain is made to be {Re(Zin)/3 - j Im(Zin)}.

Please again follow the steps:
1. Load the Source with an Open stub (or capacitor). You have a short stub (The high value capacitor is a short). When you tune the open stub look at the gate (With out the DR yet).
2. You might need to load the Drain by a low impedance or 50 ohm is O.K.
3. Tune the Open stub length at the Source while looking at S11 at the Gate port. You must see Mag(S11)>1. Tune the Stub to bring the negative resistance range at the desired frequency.
4. Add a transmision line to the gate in order to rotate the S11 curve so at the desired frequency it is a parallel resonance and a negative resistance. Curve goes from top side of smith chart to down, and at resonance it cross the axis.
5. Now add the DR model (I hope you already simulated it).
6. Now tell us it works (use oscport)

D.J

Here is what i got......... but i can't get osc..........

Is it because i set the HB parameters wrongly? Please help!