sowmiya
Newbie level 5
Hi,
I have a case wherein there are 2 defintions for the same library cell in verilog. The incorrect definition file is present in the library dir from which I read all the other files using "vcs -y <dir path> " option. But the correct file is present in a different area. I want the simulator to read this correct file and ignore the incorrect file. I tried using the `uselib directive in verilog and made it point to the correct file. But the problem here is this directive is compiled well before the lib dir is parsed and hence it takes in the incorrect file(as this is the last definition). Also, I cannot edit the incorrect file.
Is there a way to make the simulator read the 1st file and ignore all the module defintions after the 1st one is read-in?
I have a case wherein there are 2 defintions for the same library cell in verilog. The incorrect definition file is present in the library dir from which I read all the other files using "vcs -y <dir path> " option. But the correct file is present in a different area. I want the simulator to read this correct file and ignore the incorrect file. I tried using the `uselib directive in verilog and made it point to the correct file. But the problem here is this directive is compiled well before the lib dir is parsed and hence it takes in the incorrect file(as this is the last definition). Also, I cannot edit the incorrect file.
Is there a way to make the simulator read the 1st file and ignore all the module defintions after the 1st one is read-in?