Cadence layout simple question regarding current mirror and differential pair

Hi All,

Ive got 3 questions regarding layout of current mirror and differential amplifier:-

Q-1. Ive got a current mirror with the pairs having large widths such that their finger numbers are 100 and 200 ( so as to keep the finger width <10 um )... now for this if i go for common centroid it will take lots of time for routing... so my question is what can i do for matching them ... interdigitization is an option but it will lead to a long transistor structure... whereas common centroid will take huge time to even route ..?

Q-2. This question is more of a confirmation from you guys ... Statement is :- we should try to keep the finger width < 10 um while doing layout... For the case mentioned in Q-1 its 10um ... is this finger width ok?

Q-3. Do we need to put dummy pair for differential pairs too?

Thanks all.

Regards.

Q-1 : If you use Layout L then you can "break" a large transistor with lots of fingers in the respective number of multiples (it is like using the multiplicity option at the CDF properties of the transistor at the schematic side).Then
you can do this for all transistors that have the same or similar number of fingers and finally interdigitize them using a pattern after doing some floorplanning estimation and according to the matching conditions you want to achieve.

Q-2 : Since this is the direction you have for layout (i suppose from the person who gave you the specs or designed the schematic) and since this is done for schematic design then you should follow it without asking ;-)

Q-3 : It depends on the signal frequency that passes from the differential pair...if the frequency is quite large (hundreds of MHz and above) then avoid the dummies (you don't want their parasitics).

Hihi, may i know how to do interdigitize?? i have inserted two transistors one by one into layout . how should i do so that i can digitize both transistors together for matching? may i know that do i need to do modifications like adding transistor or others on my schematic? or i just need to leave schematic there having two transistors only for the current mirror? between, if my sizing of current mirror is 1:10 , can i use interdigitize or what should i do for the matching purpose? thanks