problem with gain of narrow band LNA design

i am designing Narrow band Inductive Source Degenerated LNA using NMOS and 90nm mode using adsl. i am getting proper the frequency response at 2.4GHz for s(2,1) plot but the gain is negative. i don't knw what could be casing the gain to negative. i have attached the plot both as .dds and .jpg and also the schematic of the circuit and the model. can anyone please explain to me what causes the gain to be negative? thanks

Aytan said:

i am designing Narrow band Inductive Source Degenerated LNA using NMOS and 90nm mode using adsl. i am getting proper the frequency response at 2.4GHz for s(2,1) plot but the gain is negative. i don't knw what could be casing the gain to negative. i have attached the plot both as .dds and .jpg and also the schematic of the circuit and the model. can anyone please explain to me what causes the gain to be negative? thanks

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Aytan,

Power gain is negative, it means you need to double check all DC parameters of your design. Check out, Bias current, Operating point, There is some thing seriously wrong in DC points.

girih192002 said:

Aytan,

Power gain is negative, it means you need to double check all DC parameters of your design. Check out, Bias current, Operating point, There is some thing seriously wrong in DC points.

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----------------------------------------------------------------------------------------------------------------------------------------------------thank you for replying.. but how can i adjust the Dc points? in my calculations i set ID=8mA on the simulation i get ID=340mA!!! even though i set the aspect ratios of the nMOSFETS based on the calculation of ID=8mA... what could be causing this... and would you plz tell me how to fix it....

thank u girih192992

plz any suggestions would be appreciated... since i reached a dead end ... thanks

Aytan said:

plz any suggestions would be appreciated... since i reached a dead end ... thanks

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-W/L Ratios of MOSFETs are huge for 90nm technology...Check them out...
-When you look at Vds(M1) is 350mV<<1.8V Vgs(M1) so MOS transistor is in triode region so gm is very low...Gain is low too...
-First, define a proper bias voltages and current for MOS transitors and then try to design the LNA...