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[SOLVED] How to create/enter VHDL file in Cadence using text editor

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William22

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I'm a newbie in vhdl coding and ready to learn. I want to enter vhdl file. How to create VHDL file in cadence using text editor is confusing me. Any help would be appreciated.

Thanks in advance.
 

In my opinion, this URL could help you : VHDL/Verilog Simulation Tutorial
However, your question is not very precise. Which cadence tool you are using?
Explaining more your need is a key for members to help you.


BR,
Moez
 

Hi Moez

Thanks for your reply. I am using cadence design system tool ver 1995 -2008.
I have taken to the advise and am now okay with that bit of enquiry.
Many thanks.
 

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