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how to generate scan patterns with layout netlist?

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tys

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i used Tetramax to run ATPG and generate scan patterns for a module, with synthesis netlist and corresponding tpf file.
is it feasible to do that with layout netlist?
i checked the 2 netlists, they have different ports quantity of the module. the layout netlist has more ports. i guess it is due to the PT optimaztion, buffers are inserted, right? how to run ATPG based on this layout netlist with above mentioned the tpf file?
 

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