# Can you tell why need two flipflop to synchronize the asynchronous reset ?

1. ## Can you tell why need two flipflop to synchronize the asynchronous reset ?

Hi guys.

When designing an asynchronous digital design, can you tell why need two flipflop to synchronize the asynchronous reset ?

Can we just use one flipflop to synchronize the asynchronous reset for the internal flipflop use ?

Thanks!

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2. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

two stage flipflop for asynchronous signal,remove metastability

3. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

Can you explain it more detailed ?
Thanks!

4. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

You could find on internet some article about meta stability issue in electronic design. Two flip flops is a minimal to reduce dramatically the statistic to have an issue when a signal goes from one clock domain to another one clock domain.

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5. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

You don't need to synchronize an asynchronous reset. That's why it's called ASYNCHRONOUS. It is a non-clocked signal.

6. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

Hi barry.

If you dont synchronize the asynchronous reset, how can you guarantee the reset signal can arrive at all registers within one clock cycle ?

Thanks!

7. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

Hello ..
Can metastability be avoided using fuzzy logic..
Can we afford transmission time delay of few microseconds to process the signal using fuzzy logic...

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8. ## Re: Can you tell why need two flipflop to synchronize the asynchronous reset ?

The initial question is already misleading you are obviously talking about synchronous digital designs with asynchronous reset.

You don't need to synchronize an asynchronous reset. That's why it's called ASYNCHRONOUS. It is a non-clocked signal.
The discussion is about technics rather than semantics. It's called asynchronous, because it feeds the asynchronous reset input of registers. Although it's not a clocked signal, it needs to satisfy setup and hold timing requirements, otherwise the reset result will be unpredictable. This is usually achieved by releasing the reset synchronously to clock.

If you dont synchronize the asynchronous reset, how can you guarantee the reset signal can arrive at all registers within one clock cycle ?
Yes, that's the point. The reason for the second FF is metastability avoidance, as already explained.
Can we afford transmission time delay of few microseconds
You are talking about a transmission line of a few hundred meters length. But besides affording it, it seems pretty useless.

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Thanks FVM!

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