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comparator with a single input

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TrickyDicky said:
no. Im not talking about code.
A synchronised data signal will be a double registered version of data to avoid meta-stability, assuming its completly asynchronous to the clock (if its synchronous to the clock, then there is no problem.)

You need to do something like this:

Code: 
signal data_sync : std_logic_vector(1 downto 0);

process(clk)
begin
  if rising_edge(clk) then
    data_sync <= data_sync(0) & data;
  end if;
end process;


count_proc : processs(clk)
begin
  if rising_edge(clk) then
    if data_sync(1) = '1' then
      count <= count + 1;
    end if;
  end if;
end process;

Making a process sensitive to data just means you're creating logic sensitive to the data signal (probably without registers). The above code synchronises the data signal and then uses that to measure the time its high for.
Click to expand...

sorry for being troublesome, but do you mind explaining the above code ?
 

The first process is a shift register 2 registers long. It takes in the asynchronous data signal and synchronises it to the clk domain.
The second process only counts up when the synchronised data signal is '1'.
 

Code: 
library ieee;
use ieee.std_logic_1164.all;
	

entity counter is
	port( 
		clk  : in std_logic;
		data : in std_logic;
		enable  : in std_logic;
	    dout : out std_logic; 
		
	);
end counter;

architecture count of counter is

signal data_sync : std_logic_vector(1 downto 0);
signal pre_count : integer;
signal pre_count_1 : integer;
signal pre_count_2 : integer;
signal data_count : integer;

begin
	process(clk)
	begin
		if rising_edge(clk) then
			data_sync <= data_sync(0) & data;
		end if;
	end process;


	count_proc : process(clk, enable)
	begin
		if (enable = '0') then
			data_count <= 0;
		elsif (data_sync(1) = '1') then 
			pre_count <= 0;
		end if;
		
		if rising_edge(clk) then
			pre_count <= pre_count + 1;
		end if;	
	end process;
	
	if (data_count = 0) then
		pre_count_1 <= pre_count;
		data_count <= data_count + 1;
	elsif (data_count = 1) then
		pre_count_2 <= pre_count;
		data_count <= data_count - 1;
	end if;

	compare_proc : process(clk, pre_count_1, pre_count_2)
	begin
		if rising_edge(clk) then
			if (pre_count_1 > pre_count_2) then
				dout <= '1';
			elsif (pre_count_1 < pre_count_2) then
				dout <= '0';
			end if;
		end if;
end count;

hi, how should i modify the above code such that after the first 2 process it will do the if statement then do the compare_proc process ?
 

processes run in parrallel, you cannot make them run one after the other.
You also have code outside a process that needs to be inside a process (looking at it, it needs to be in the count_proc)
 
hi, i ran the simulation for the above code and i noticed that for data_sync(1) = '1' , pre_count only changes to 0 at the middle of data_sync(1) , what should i modify such that pre_count will change at the rising edge of data_sync(1) ?
 

is data sync synchronous to the clock? what does the testbench code look like?
 

i used active-HDL to do simulation, is the testbench necessary ?
 

Yes. You have far more control over the input.
COuld you post a waveform showing the problem?
 

Untitled.png

thx for the help.
 

Where did the inputs get generated?
Looking at this code it shouldnt jhave a big effect as its the value at the rising edge of the clock thats important, but it might be safer to generate your own testbench.
 

The simulator allowed me to determine the input parameters
 

ur code also run in modelsim and compile successful........
 

hi, i faced another simulation problem with my code, as seen in the attached image, the data_count changes from 0 to 1 and then from 1 to 0 immediately, however, i only require it to change from 1 to 0 on the next data_sync (1) = '1', what's causing this immediate change in data_count ?Untitled.png
 

-- Post #23 snippet
"count_proc : process(clk, enable)
begin
if (enable = '0') then
data_count <= 0;
elsif (data_sync(1) = '1') then
pre_count <= 0;
end if;

if rising_edge(clk) then
pre_count <= pre_count + 1;
end if;
end process;

if (data_count = 0) then
pre_count_1 <= pre_count;
data_count <= data_count + 1;
elsif (data_count = 1) then
pre_count_2 <= pre_count;
data_count <= data_count - 1;
end if;"
---#23 Ends here
Assuming that you have modified the above code like below
"count_proc : process(clk, enable)
begin
if (enable = '0') then
data_count <= 0;
elsif (data_sync(1) = '1') then
pre_count <= 0;
end if;

if rising_edge(clk) then
pre_count <= pre_count + 1;
end if;
if (data_count = 0) then
pre_count_1 <= pre_count;
data_count <= data_count + 1;
elsif (data_count = 1) then
pre_count_2 <= pre_count;
data_count <= data_count - 1;
end if;"
end process; --- end process is moved below
In the above case "data_count = 1" will be sampled whenever there is a change in "clk". So below part of code will be triggered
"elsif (data_count = 1) then
pre_count_2 <= pre_count;
data_count <= data_count - 1;
end if;"

Make "data_count" to change with only one "if -elsif -else" Statement not with separate if - else statements
 

Shanmugaveld - You post and code does not make any sense.
 

As per my understanding because of the "clk" which is in the sensitivity list and
"elsif (data_count = 1) then --- condition changes the data_count to "0'
pre_count_2 <= pre_count;
data_count <= data_count - 1;
end if;"
@TrickyDicky
I would like to understand where i went wrong in my description
 

the template for a synchronous design with async reset is:

Code: 
process(clk, reset)
begin  
  if reset = '1' then
    --async reset
  elsif rising_edge(clk)
    --do sync
  end if;
end process;

if you deviate from this, you're likely to have problems. You should only have 1 if/elseif branch with no else. Just having clk in the sensitivity list does NOT synchronise it, as the synthesisor ignores the list, it is only used in simulation.

Also - use the code tags on the forum - it makes code easier to read. The code you posted is a mess.
 

if i have 2 if statements within a process, will they be executed concurrently or sequentially ?
 

All VHDL code in a process is executed Sequentially. But remember the difference between signals and variables - when a signal is assigned, it is only scheduled for assignment the next time the process suspends. So it will take the last assignment given to it:

Code: 
process(clk)
begin
  if rising_edge(clk) then
    a <= "000";
    a <= "001";
    a <= "010";
  end if;
end process;

A will always be "010", and it will never be "000" or "010"

Now look at a similar process with a variable:


Code: 
process(clk)
  variable a : std_logic_vector(2 downto 0);
begin
  if rising_edge(clk) then
    a := "000";
    op1 <= a;

    a := "001";
    op2 <= a;

    a := "010";
    op3 <= a;
  end if;
end process;

op1, 2 and 3 are all different values now, because variables are assigned immediatly.

So, it will all come down to behaviour. What do you intend to do with these two if statements? if they both contain asignments to the same signal, the 2nd one has priority.

Code: 
process(clk)
begin
  if rising_edge(clk) then
    a <= "00";

    if ip1 = '1' then 
      a <= "01";
    end if;
   
    if ip2 = '1' then
      a <= "11";
    end if;
  end if;
end process;

In this code, when ip1 and 2 are '0', a = "00". When ip2 = '1', a = "11", regardless of ip1. This code is equivolent to (and should compile to the same logic as):

Code: 
process(clk)
begin
  if rising_edge(clk) then

    if ip2 = '1' then
      a <= "11";
    elsif ip1 = '1' then 
      a <= "01";
    else
      a <= "00";
    end if;
   
  end if;
end process;
 
what will happen if the 'if' statement has 3 conditions meaning , one 'if' and 2 'elsif', and 2 or more are fulfilled at the same time ?
 

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