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Regarding the simulation for the vhdl code for counter using ISE

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prakashvenugopal

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Hi,

How to do simulation for this vhdl code using ISE 10.1.

entity counter is
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0));
end counter;

architecture Behavioral of counter is
signal count: std_logic_vector(3 downto 0) := "0000";
begin

process(clock)

begin
if clock ='1' and clock'event then
if enable = '1' then
count <= count + 1;
end if;
end if;
end process;
Q <= count(3 downto 0);
end Behavioral;

thanks,
V. Prakash
 

I don't understand your question. You would simulate this using a simulator like modelsim, activeHDL, etc.
 

ISE has its own simulator, but Im not sure when it started shipping. The newest version is 13. Try updating to that. Read the manual on how to use it.
 

Hi,

I am using ISE 10.1. what is the Procedure for simulation? Any simple document to do simulation? please share

Thanks,
V. Prakash
 

Don't know about 10.1. Oldest I kept installed is 11.1. As TrickyDicky pointed out, modern versions of ISE come with their own simulator (ISim).

When you create a new project, you can select what simulator you want to use. So check that (or the documentation) to see if 10.1 has ISim for simulation. If it doesn't have ISim yet, you could get a trial license for Modelsim. Modelsim support in ISE has always been good IMO.

---------- Post added at 08:18 ---------- Previous post was at 08:17 ----------

Upon further reading ... is this your first testbench ever? Or just having problem in ISE specific?
 

Hi,

Yes.This is my first testbench. Need some simple document how to do simulation?

Thanks,
V. Prakash
 

this code is not a testbench, it looks more like a design that you would test within a testbench.
I suggest you get a newer version of ISE, or get a free version of modelsim (or any other simulator). Then read the simulator manual on how to run a simulation in that tool.
 
Hi,

Yes. it is a design code. not a testbench code. I had downloaded the Modelsim student version. For simulation, we have to write testbench? without writing the test bench, we cant simulate the code.? If yes, how to write test bench to simulate that 4 bit counter code. Please do let me know with some example.

Thanks,
V. Prakash
 

the test bench needs to generate the clock and enable signal. Something like this:

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_tb is 
end entity;
  
architecture test of counter_tb is
  signal clk    : std_logic := '0';
  signal enable : std_logic;
  
  signal q      : std_logic_vector(3 downto 0);
begin
  
  clk    <= not clk after 10 ns;  --50 Mhz
  enable <= '1', '0' after 1 us;
  
  uut : entity work.counter
  port map (
    clock  => clk,
    enable => enable,
    q      => q
    );
  
end rtl;
 
Hi,

In Xilinx ISE 10.1, in the source window, source for: behavioural simulation is selected.
In process window, under Xilinx ISE simulator, behavioural check syntax is clicked to check the syntax of below test bench for 4 bit counter:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_tb is
end entity;

architecture behavior of counter_tb is
signal clk : std_logic := '0';
signal enable : std_logic;
signal q : std_logic_vector(3 downto 0);

begin

clk <= not clk after 10 ns; --50 Mhz
enable <= '1', '0' after 1 us;

uut : entity counter_tb
port map (
clk => clk,
enable => enable,
q => q
);

end behavior;


It show the error as:
ERROR:HDLCompiler:435 - "counter_tb.vhd" Line 22. Formal clk is not declared
ERROR:HDLCompiler:854 - "counter_tb.vhd" Line 10. Unit behavior ignored due to previous errors


what may be the cause for it? Please let me know.

Thanks,
V. Prakash
 

you're going to have to do your own debugging one day you know. This is as basic as it gets.

Change
clk => clk,

to
clock => clk
 

Hi,

Yes. i had tried with clock => clk also.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_tb is
end entity;

architecture behavior of counter_tb is
signal clk : std_logic := '0';
signal enable : std_logic;
signal q : std_logic_vector(3 downto 0);

begin

clk <= not clk after 10 ns; --50 Mhz
enable <= '1', '0' after 1 us;

uut : entity counter_tb
port map (
clock => clk,
enable => enable,
q => q
);

end behavior;



It is showing the same error as:
ERROR:HDLCompiler:435 - "counter_tb.vhd" Line 22. Formal clk is not declared
ERROR:HDLCompiler:854 - "counter_tb.vhd" Line 10. Unit behavior ignored due to previous errors

Thanks,
V . Prakash
 

you didnt copy my code correctly. You forgot the library reference when instantiating the counter. The UUT you are trying to instantiate the is the testbench, which has no ports (and you'd end up with an testbench instantiating itself to inifinity)

uut : entity work.counter

NOT counter_tb
 
The problem is about elementary semantics of VHDL design and test benches, I think.

I guess, you want to instantiate the counter design under test, as shown in the example in post #9. But you are instantiating the test bench itself. Unfortunately this would a) cause infinite recursion b) can't work because the test bench has no port signals ("Formal clk is not declared"). Please reconsider.

entity counter_tb is
end entity;
...
uut : entity counter_tb
port map (
Click to expand...
 
Hi,

Under Xilinx ISE simulator, there is a option called simulate behavioural model. After clicking that, i had a simulation screen like which i had attached. In this screen, by adjusting the blue marker, i can see the counter Q value gets incremented. The enable is continously ON. How to dessert the enable.? How to make enable= '0' in the simulation?. what is the procedure to make changes in it. Please let me know.

Thanks,
V. Prakash

https://obrazki.elektroda.pl/41_1324701002.jpg
 

change the testbench code. Theres where enable is set.
 

Hi,

enable <= '1', '0' after 1 us;
Click to expand...

This code will keep enable high for 1 usec and keep the enable low for ever.
I have to made the enable signal: On time = 844.2 usec and OFF time= 145.2 usec so on...continuously....
How to change the above code for this?

Thanks,
V. Prakash
 

try using a process:

Code: 
process
beign
  enable <= '1';
  wait for 844.2 us;
  enable <= '0';
  wait for 145.2 us;
end process;
 
Hi,

I did the simulation with Dual Port RAM connecting

1) 8 bit counter address_in --> to 1st RAM Address_in Port
2) 8 bit counter address_out--> to 1st RAM Address_out Port
3)8 bit data counter --> to 1st RAM Data_in port. (in this case, data will be fed from the 8 bit counter instead of external microcontroller)

For 1 RAM interface, the simulation is working fine.

I try to interface 2nd Dual port RAM connecting the

1) Same 8 bit counter address_in --> to 2nd RAM Address_in Port
2) Same 8 bit counter address_out--> to 2nd RAM Address_out Port
3) Same 8 bit data counter --> to 2nd RAM Data_in port. (in this case also, data will be fed from the 8 bit counter instead of external microcontroller)

Even after interfacing the 2nd dual port RAM, in the simulation Screen there is no signal seen for 2nd RAM. Only 1st RAM signal only seen in the simulation screen. Please refer the simulation screen attached. I am able to see the signal of 2nd RAM in sim objects under process window. refer the attachment mark. but, there is no signal seen in the simulation screen. what may be the cause for this problem. Please do let me know.

This is my testbech code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram_tb IS
END ram_tb;

ARCHITECTURE behavior OF ram_tb IS

-- Component Declaration
COMPONENT ram_simple1
PORT(
clk_in : in std_logic;
clk_out : in std_logic;
we : in std_logic;
addr_in : in std_logic_vector( 7 downto 0);
addr_out : in std_logic_vector( 7 downto 0);
data_in : in std_logic_vector( 7 downto 0);
data_out : out std_logic_vector( 7 downto 0));
END COMPONENT;

COMPONENT read_counter
PORT(
clock : in STD_LOGIC;
enable : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0));
end component;

COMPONENT data_counter
PORT(
clock1 : in STD_LOGIC;
enable1 : in STD_LOGIC;
Q1 : out STD_LOGIC_VECTOR(7 downto 0));
end component;

COMPONENT write_counter
PORT(
clock2 : in STD_LOGIC;
enable2 : in STD_LOGIC;
Q2 : out STD_LOGIC_VECTOR(7 downto 0));
end component;


COMPONENT ram_simple2
PORT(
clk_in1 : in std_logic;
clk_out1 : in std_logic;
we1 : in std_logic;
addr_in1 : in std_logic_vector( 7 downto 0);
addr_out1 : in std_logic_vector( 7 downto 0);
data_in1 : in std_logic_vector( 7 downto 0);
data_out1 : out std_logic_vector( 7 downto 0));
END COMPONENT;

signal clk_in : std_logic := '0';
signal clk_out: std_logic := '0';
signal we: std_logic;
signal addr_in : std_logic_vector(7 downto 0);
signal addr_out : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);

signal clock : std_logic := '0';
signal enable: std_logic;
signal Q: std_logic_vector(7 downto 0);

signal clock1 : std_logic := '0';
signal enable1: std_logic;
signal Q1:std_logic_vector(7 downto 0);

signal clock2 : std_logic := '0';
signal enable2: std_logic;
signal Q2:std_logic_vector(7 downto 0);

signal clk_in1 : std_logic := '0';
signal clk_out1: std_logic := '0';
signal we1: std_logic;
signal addr_in1 : std_logic_vector(7 downto 0);
signal addr_out1 : std_logic_vector(7 downto 0);
signal data_in1 : std_logic_vector(7 downto 0);
signal data_out1 : std_logic_vector(7 downto 0);

constant clk_period : time := 62.5 ns;


BEGIN
-- Component Instantiation
uut: ram_simple1
PORT MAP(
clk_in => clk_in,
clk_out => clk_out,
we => we,
addr_in => addr_in,
addr_out => addr_out,
data_in=> data_in,
data_out => data_out
);


uut1: read_counter
PORT MAP(
clock => clock, -- clock,
enable => enable,
Q => Q
);

uut2: data_counter
PORT MAP(
clock1 => clock1,
enable1 => enable1,
Q1 => Q1
);

uut3: write_counter
PORT MAP(
clock2 => clock2,
enable2 => enable2,
Q2 => Q2
);

uut4: ram_simple2
PORT MAP(
clk_in1 => clk_in1,
clk_out1 => clk_out1,
we1 => we1,
addr_in1 => addr_in1,
addr_out1 => addr_out1,
data_in1=> data_in1,
data_out1 => data_out1
);

addr_in <= Q2;
data_in <= Q1;
addr_out <= Q;

addr_in1 <= Q2;
data_in1 <= Q1;
addr_out1 <= Q;

enable2 <= we;
enable1 <= we;
enable <= not enable2;


clk_process :process
begin
clk_in <= '0';
wait for clk_period/2;
clk_in <= '1';
wait for clk_period/2;
end process;

clk_process1 :process
begin
clk_out<= '0';
wait for clk_period/2;
clk_out <= '1';
wait for clk_period/2;
end process;

clk_process2 :process
begin
clock<= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;

clk_process3 :process
begin
clock1 <= '0';
wait for clk_period/2;
clock1 <= '1';
wait for clk_period/2;
end process;

clk_process4 :process
begin
clock2 <= '0';
wait for clk_period/2;
clock2 <= '1';
wait for clk_period/2;
end process;

clk_process5 :process
begin
clk_in1 <= '0';
wait for clk_period/2;
clk_in1 <= '1';
wait for clk_period/2;
end process;

clk_process6 :process
begin
clk_out1 <= '0';
wait for clk_period/2;
clk_out1 <= '1';
wait for clk_period/2;
end process;

write_enable_process: process
begin
we <= '1';
wait for 16 us;
we <= '0';
wait for 16 us;
end process;

write_enable1_process: process
begin
we1 <= '1';
wait for 16 us;
we1 <= '0';
wait for 16 us;
end process;

end behavior;

Please let me know did i made mistake in the test bench code.?

Thanks,
V. Prakash



https://obrazki.elektroda.pl/31_1325053608.jpg
 
Last edited:

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