physical design essentials and requirement

1. what are the different types of libraries that are used in physical design?
2. What are the input & output file formats(extension) that are involved in physical design?
3. What does floor planning mean?
4. What does power planning mean?

hai pavithra,
1. In PD we will use bestcase, worstcase and typical library. Based on pvt(process voltage and temperature) It will be defined...

2. There PD process is divided into synthesis, pnr, signoff etc... so based on that the input will differ.... let me explain two for example

For synthesis:-

Input requirements :-
1.RTL (.v file)

2. .lib file (worstcase.lib)

3. .sdc file (synopsys design constraint)

Output :- .v file (netlist)

For pnr :-
Input requirements :-

1 .v file (netlist)

2. .sdc file

3. .lib (worstcase bestcase typical)

4. both metal information .lef and cell information .lef is needed (library extract format)


output :-
def, lef, gds

gds is the main thing



3.Floorplaing :-
Its the initial thing in place and route(pnr).. Floorplanning is deciding our physical design based of our design.. you can get abou this in google itself..

4. Power planning:-
power planning deals with how much power is needed for your current design. google it you will get more..


Floor planning and power planning will differ based on our requirements in project level..

Thanks this may help you...:razz:

what does def,lef,pnr stands for

Pnr stand for place and route. This is commanly used term for physical design flow. Library Exchange Format (LEF) is a specification for representing the physical layout of an integrated circuit in an ASCII format. It includes design rules and abstract information about the cells. LEF is used in conjunction with Design Exchange Format (DEF) to represent the complete physical layout of an integrated circuit while it is being designed.

def and lef are format of files... Library Exchange Format (LEF) and Design Exchange Format (DEF)


pnr is process after synthesis (i.e) place and route process... Here we do floorplan placement cts and routing Here the inputs are taken and the output will be in physical layout format (diagramtic connection of cells and metal layers)

ex;- There are different types of tool for pnr

EX ;- encounter tool from cadence....

Hope this may help u.. thanks :razz:

what are ignore pins and sync pins?
What is insertion delay & hw does it exsists?

For insertion delay check below link. Please elaborate your questions?
ASIC-SoC-VLSI Design: Clock Definitions

Hai pavithra,

Insertion delay is the delay in the clock path.

In the sense, "the delay from clock tree starting point to the the flop". network delay

Main thing its deals with clock delay.


Ignore pins: -

Ignore pins are the mark pins that do not need to be balanced during clock tree synthesis.. Also it is called as stop pins.

Ignore pins can be explicit or implicit

Synchronous pins:-

Synchronous pins are pins whose source are same.

i.e starting point is same.

Hope this may help u a bit.. Thanks:razz:

How power planning is done in physical design?
What are the prespectives, algoritham involved in power planning?
What are the steps, libraries involved?
How can it be optimised?

---------- Post added at 07:38 ---------- Previous post was at 06:15 ----------

Why are pads required for i/o ports.
what are the difference betwen power rings & straps & trunk?

hai pavithra

How power planning is done in physical design?
power planning is done based on the IR drop of your project design..If the IR drop is high then u need more number power straps.

What are the prespectives, algoritham involved in power planning?
normally we will use tool to calculate IR drop etc.., Tool ex:- voltage storm

How can it be optimised?
power can be optimized according to the design u need..... E:- u can use low voltage cells or else if Ir drop is very low u can neglect some of the power straps.

Ex:- if your design is small u will not need much power straps...

Why are pads required for i/o ports.
Pads are required in io/ports to make the connection to next level things.. Generally IO pad will not have effect on timing...

what are the difference betwen power rings & straps & trunk?
power rings are vdd and vss ring (i.e top supply ring).. The power straps are vertical and horizontal lines which is connected to power rings.... (Taking the supply from power rings )..

This may help u.. Thanks:razz:

How to calculate the width of power ring?
How core cell power management & i/o cell management is done?
How to minimise the ir drop? Any methods?

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How to calculate IR drop of the design?

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What is antenna effect?
How does IP differ feom being used in block level & in full chip level?

Hai pavithra,
The width of the power ring is calculated by
Resistance =voltage/current

width of the power ring = (Half Length /Resistance) * sheet resistance of the specificmetal

EX:- (If u are design has length 100 and width 100 then the length value is 100/2 =50)

U can calculate the IR drop tool EX;-Voltage Storm tool we will not calculate it manually........


Antenna effect:-
antenna effect occurs when lengthy metal is connected to the poly... to avoid this u can shorten the metal by adding vias i.e (metal jog) or u can use antenna diode (As soon as enough charge is induced onto the
metal by the antenna effect, the diode diverts the charge to the substrate )..

Antenna effect results to gate damage..

This may help a bit.... thanks :razz:

Check these links:
https://www.edaboard.com/threads/119661/#post922734
https://www.edaboard.com/threads/217088/#2
https://www.edaboard.com/threads/234001/#3
https://www.edaboard.com/threads/179239/
https://groups.google.com/forum/#!s...ct/vlsi-design-forum/6RQWVTQ_Sh0/fLkBDPwEpWsJ

What & how technology migration is done?
What are advantages and disadvantges of technology migration?

---------- Post added at 05:45 ---------- Previous post was at 05:43 ----------

How place & route is done?
What are the file formats involved in each stages of physical design?

What does the physical view of a design mean?

---------- Post added at 07:47 ---------- Previous post was at 06:12 ----------

Why pads should have high capacitence?

How place & route is done?
Place is route is based on the path based selection of the logical element and I/O Pads based the contstant that are given to route the required digitial path.
Why pads should have high capacitence?
Because in the ditigial electronics if low capacitances are there they may dischage the charge store on the PADS and most of the case the signals enters from the pad to the digital designs.

hi,

milind.a.kulkarni said:

How place & route is done?
Place is route is based on the path based selection of the logical element and I/O Pads based the contstant that are given to route the required digitial path.
Why pads should have high capacitence?
Because in the ditigial electronics if low capacitances are there they may dischage the charge store on the PADS and most of the case the signals enters from the pad to the digital designs.

Click to expand...

can you please elaborate on "Why pads should have high capacitance??" ........

---------- Post added at 13:57 ---------- Previous post was at 13:56 ----------

hi,

pavithra226 said:

What does the physical view of a design mean?

---------- Post added at 07:47 ---------- Previous post was at 06:12 ----------

Why pads should have high capacitence?

Click to expand...

Physical view is also called the layout view, this is the lowest level of design abstraction in common design practice. From a manufacturing perspective, the standard cell's VLSI layout is the most important view, as it is closest to an actual "manufacturing blueprint" of the standard cell. (In this view you can see internal connections of a transistor, its pins and the different diffusion regions).

---------- Post added at 14:19 ---------- Previous post was at 13:57 ----------

What are file format involved in different stages of physical design?

Floor planning :- U need to add the .v (verilog netlist), .lib, .tech, .lef files. If you will give these files as input to the tool, the tool will give u the frame view of the standard cell ,macros associated with the design. When this is done you can extract summary report (.summary file) for estimating your die size and doing power planning.

Placement :- now .sdc file additionally has to be added in your config file.

CTS :- now you will give clock tree synthesis file as a input to the tool (.ctstch file), which has the information on preferred metal layers, buffers which can be used etc.

and you can extract .def and .lef as an output after each step from the tool (this may be helpful while switching from one tool to other after any step). When you will be done the final file which matters and has complete information of the mask is GDS file.