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Placement of Termination Resistor

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kathiresan

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i would like to ask a simple question where we have to put the series & Parallal (Pull Up & Pull Down) termination resistor????:idea:
 

see it is based on the devices that you used.....

Generally for memory devices terminations are at receiver end means at memory
where are for I2C kind of devices it is better that they are at the transimmter end means at the micro-controller...

Also one need to do proper SI analysis in case of you are planning to use it for minimizing the reflection/ cross talks etc....

Good Luck
 

Pull-up and Pull-down are different from series and parallel terminations..
Pull-up and Pull-down resistors are used to make the signal high and low w.r.t the resistor value..
Terminations methodology is for signal integrity or delay corrections
 

In my experiences .....In the DDR kind of interfaces you have even pull-up and pull-down interfacing for Clock lines DSQ signals based on your SI.....at least I had used them......in these cases these termination comes in the receiver end i.e. at memory end....apart from series and parallel teminations....
 

i am doing a PCIe card in that for address bus pull up resistor are used where should i need to place those resistor?
address bus travel from connector to controller
 

PCIe doesn't involve an address bus. Please clarify your question.
 

kathiresan, as FvM rightly mentioned there will not be Address/Data bus differentiation in PCI-Express. Secondly you are talking about VTT terminations on a DDR address bus. These two are completely unrelated to each other.

VTT terminations on DDR (rather SSTL interface) is for a different reason- mainly to take care of Sink and source current requirements of DDR buffers. They are needed more from the functionality point of view.

And coming to Parallel terminations (actually VTT terminators) & Series termination- VTT terminators will be close to the DDR memories on the Address bus and Series terminators will be close to the controller/processor
 
Secondly you are talking about VTT terminations on a DDR address bus.
Click to expand...
I assume, that you're guessing right. But the original poster didn't mention DDR RAM at all.
 

i have never done any PCI or PCIe so can you explain? customer have mentioned it as PCIe
 

PCIe (PCI Express) is a serial bus with lanes (typical only 1 ) of differential Rx and Tx pairs. The shown signals are not directly related to PCIe, they rather look like a PCI or similar parallel bus. If your design involves a general purpose PCIe interface chip, it possibly exposes the said signals as local bus.
 
thanks for the reply guys its useful for me. i'll ask even more doubts that have. once again thanks for sharing thing with me:-D
 

Get Howard Johnsons book High-speed digital design:
But basic rules are:
Series termination next to the driving pin, as close as possible.
Parallel termination at the receiving end.
The rest is covered in detail by such people as Howard Johnson and Eric Bogatin.
 
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