# Sequence generator in verilog????

1. ## Sequence generator in verilog????

Hi ...
i want to generate 'q' strings of 0's followed by 1 and this i want to implement using verilog.
me not getting how to implement it as output is variable number of bits.
can anybody help me in this to get it in veriog??

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2. ## Re: Sequence generator in verilog????

if you r talking abt PRBS(Pseudo Random Binary Sequence) generator, u should specify how many bits or the length . If u want n- bit PRBS generator ,then it can give u 2^n-1 binary sequences.
For PRBS FPGAsRus PRBS which are usually implemented using an LFSR(linear Feedback Shift register) i.e shift register with linear feedback.
.......hope it helps

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3. ## Re: Sequence generator in verilog????

Originally Posted by antaryami.mt.er09
if you r talking abt PRBS(Pseudo Random Binary Sequence) generator, u should specify how many bits or the length . If u want n- bit PRBS generator ,then it can give u 2^n-1 binary sequences.
For PRBS FPGAsRus PRBS which are usually implemented using an LFSR(linear Feedback Shift register) i.e shift register with linear feedback.
.......hope it helps
this is not what i exactly want. actually i want to implement 'Golomb rice coding' in verilog.
In this two numbers are there for example N and M.N/M is calculated. Now any quotient q i get. That q i have to encode using unary coding.
Unary coding is implemented by q string of 0's followed by 1.
for example if q=2 then i hv to get unary code as '001'.
problem is that q can be anything and hence unary code length is not fixed. so i dnt think its possible with help of LFSR.
so plz help me how to implement unary code in verilog.

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4. ## Re: Sequence generator in verilog????

No idea. I would suggest to get the algo 1st and then write it in C or Matlab , then to verilog .

5. ## Re: Sequence generator in verilog????

Originally Posted by antaryami.mt.er09
No idea. I would suggest to get the algo 1st and then write it in C or Matlab , then to verilog .
i hv implemented that in matlab.i understood steps also for tht algorithm.now i started implementing it in verilog so i stuck at that point.

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