a program to output a specified image to a stream of integers for VHDL file input

The control always has to be done at the input. But with this code you could connect the output from this code to another instantiation of the moving average, and it will halve the data rate again.

yes you can, but without the valid signals, how do you know when the data is correct?

Hi TrickyDicky,

You are right, during write the testbench code I realise that how the signal will give the right input value.
I need to assign input (source_pixel) to the signals (ip1,ip2,ip3,ip4). How to do this? My idea is like the code below, but I think it is not the exactly in the right way. Can you give a suggestions? Thanks for reply..

if rising_edge(clk) then

source_pixel <= ip1;
source_pixel <= ip2;
source_pixel <= ip3;
source_pixel <= ip4;

end if;

you have connected ip1/2/3/4 to the source_pixel input of each block, so you assign values to them. You have no visibility of source_pixel (and it would be confusing anyway because you have 4 of them).

just do it like this:

ip1 <= a;
ip2 <= b;

etc

Hi TrickyDicky,

I have write main vhdl code that contains of two moving_average component. When I simulate in ModelSim, the waveform only shows the values of source_pixel, the rest is "XXXX..". Its seems like the input source_pixel not connected with the signals. Below is the main code,can you check it? Many thanks..

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library ieee_proposed;
use ieee_proposed.fixed_pkg.all;

entity average is
generic (IN_HIGH : integer := 3;
IN_LOW : integer := -4);
port (clk : in std_logic;
reset : in std_logic;
source_pixel : in sfixed(IN_HIGH downto IN_LOW);
source_pixel_valid : in std_logic;
av_out : out sfixed(IN_HIGH downto IN_LOW-2);
av_out_valid : out std_logic);
end average;

architecture rtl of average is

component moving_average_one is
port (clk : in std_logic;
reset : in std_logic;
source_pixel_one : in sfixed(IN_HIGH downto IN_LOW);
source_pixel_valid_one : in std_logic;
av_out_one : out sfixed(IN_HIGH downto IN_LOW-1);
av_out_valid_one : out std_logic);
end component;

component moving_average_two is
port (clk : in std_logic;
reset : in std_logic;
source_pixel_two : in sfixed(IN_HIGH downto IN_LOW-1);
source_pixel_valid_two : in std_logic;
av_out_two : out sfixed(IN_HIGH downto IN_LOW-2);
av_out_valid_two : out std_logic);
end component;

signal a,b,c,d : sfixed(IN_HIGH downto IN_LOW);
signal n1,n2,n3,n4 : sfixed(IN_HIGH downto IN_LOW-1);
signal ip1,ip2,ip3,ip4 : sfixed(IN_HIGH downto IN_LOW);
signal op1,op2 : sfixed(IN_HIGH downto IN_LOW-1-1);
signal m1,m2,m3,m4,m5,m6 : std_logic;
signal x1,x2,x3,x4,x5,x6 : std_logic;

begin

--stage one--
A1 : moving_average_one
port map (clk,reset,ip1,m1,n1,x1);

A2 : moving_average_one
port map (clk,reset,ip2,m2,n2,x2);

A3 : moving_average_one
port map (clk,reset,ip3,m3,n3,x3);

A4 : moving_average_one
port map (clk,reset,ip4,m4,n4,x4);

--stage two--
A5 : moving_average_two
port map (clk,reset,n2,m5,op1,x5);

A6 : moving_average_two
port map (clk,reset,n4,m6,op2,x6);

average_proc : process (reset,clk)
begin
if reset = '1' then

av_out <= "0000000000";

elsif rising_edge (clk) then

ip1 <= a;
ip2 <= b;
ip3 <= c;
ip4 <= d;

av_out <= op1;
end if;
end process;
end rtl;

Source_pixel is an input to this file, which is not connected to anything. Also a,b,c,d are not connected to anything...

Hi TrickyDicky,

How to connect the source_pixel with the signals ip1/2/3/4?. As you said before, if I assign source_pixel <= ip1/2/3/4 it would be confusing. Thank for reply..

you'll have to do it via some kind of mux. You'll need an external select.

Hi TrickyDicky,

Is it I need add a component of mux in the main code? Or just add an external select to control the input source_pixel? I try to write select code in the main code like below, but I start confusing when load the inputs in testbench. Can you help me..thank you

case S is
when "00" => source_pixel <= a;
when "01" => source_pixel <= b;
when "10" => source_pixel <= c;
when "11" => source_pixel <= d;
end case;

Fanwel - I suggest you go and read a VHDL tutorial. This thread is turning into me doing your assignment for you. You need to learn about basic digital logic concepts, that you need before you even start writing ANY VHDL.

Hi TrickyDicky,

I am sorry, I did not mean to let you do my assignment. I just want you to guide me besides I also using other materials. I have write the main code to control the input source_pixel that containing two average_moving components. There is no problem when I compile it in Quartus but, an error said "Case statement choices cover only 4 out of 81 cases" when I try to simulate it in ModelSim. I attach the main code,can you check it and tell me where I am wrong? Need your helps and again sorry..

std_logic have 9 possible values.
A case statement must cover all posibilities.
In your case statement you only cover 4 values (you dont cover when the std_logic_vector is "UU", "XX", "U1" etc).
To solve this, add a when others at the end, I suggest:

when others => Z <= (others => 'X');

This will show you theres a problem in simulation. It will be ignored for synthesis.

Hi TrickyDicky,

Is it I control the input source_pixel in the right way? Thank for your helps..

what about m1, m2 etc?

Hi TrickyDicky,

I do not control the m1,m2 etc..I just write source_pixel_valid <='1' in the main code because I think it would control them. Please correct me if I am wrong,thank for your helps..

with the currect code, m1,m2 etc are disconnected and so the moving averagers wont work (they use the valid as a clock enable). You cannot hold them at '1' unless they get a new input every clock cycle (your code provides a new input every 4 clocks). You need to synchronise the valids with the data.

Hi TrickyDicky,

Can I synchronise the valids using external select which mean write another case statement? (2 cases in 1 process)
Thank for your helps..

you can use the same case statement.

Did you try going back to a VHDL and digital logic tuturial yet (im guessing not)?

Your code is flawed. You are not connecting the inputs of the components at all (as shown in the simulation). You are trying to assign Z with the ip1/2/3 etc, but ip1/2/3 are not connected to anything. You then override them all with the final Z assignment.

Stop compiling the code in quartus - it is meaningless unless it works in modelsim.

try this process:

Hi TricyDicky,

Thank you very much for your helps..I appreciate it.