Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Signal Integrity Problem for DDR2 SDRAM and DSP in Altium - Top Signal Level value

Status
Not open for further replies.

neopisha

Junior Member level 2
Joined
Nov 30, 2011
Messages
23
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Activity points
1,440
Hi, I am trying to analysis Signal Integrity for a DDR2 SDRAM and OMAPL138 in Altium. There is a problem with signal levels. I've set the Signal Top Value rule to 1.8V for desired nets but in the simulation the default 5V top level signal is injecting. How can I change this value to 1.8V?
I've tried Signal Top Value and Base Value rules and I've edited individual pins but still 5V pulse is injecting!!!!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top