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generated clocks in synthesis

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honey13

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Hi all,

When do we define generated clocks? Do we need to define the pll outputs as generated clocks during synthesis.I am using design compiler for synthesis.


Some one help me plz.
 

Generated clocks are the clocks that have their source within the chip. In your case, for PLL clocks, I dont think you need to define generated clock definitions.
 

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