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[SOLVED] setting initial voltage in cadence for designing SRAM

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avishek_sinha_roy

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i have designed a static RAM circuit(32 nm). I wanted to perform simulation for read operation. So i needed to set the bit lines to vdd(0.9v). I used nodeset command to set the initial volatge of bitline to vdd, but the initial voltages remain upto 0.35 volt. So can u tell me what is going wrong or should i use another command if any to set the initial volatges of bit line to vdd i.e 0.9v. THANX IN ADVANCE.........
 

IC can be fine for a single cell or a few, but tedious for a RAM
block of much size.

You might consider adding trivial conductances to the RAM
unit cell, like 1E9 up on one node of the cross-coupled pair
and 1E9 down on the other. This might have enough influence
to steer the decision yet not impact operation (regen gain,
timing, leakage) meaningfully. If the resistor conductance is
greater than the "off" FET conductance then it ought to be
effective.
 
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