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Dual Port Distributed RAM VHDL Code and IP Core Xilinx

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akeedthe

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Hi All,

Im trying to come up with a Dual Port Distributed RAM - one made using the Xilinx IP Core and test it against one made by me from scratch.

Ive followed some of the example code given by Xilinx (for my own)

process (<clock>)begin
if (<clock>'event and <clock> = '1') then
if (<write_enable> = '1') then
<ram_name>(conv_integer(<write_address>)) <= <input_data>;
end if;
end if;
end process;


<ram_output> <= <ram_name>(conv_integer(<read_address>));
Click to expand...

But specially in the IP Core I tried as attached files of my toplevel and testbench. Im confused between what I get on the SPO and DPO port.

Please advice.

PS- append the .txt files back to .vhd to open
 

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  • tb_toplevel_dpramxi.vhd.txt
    4.6 KB · Views: 69
  • toplevel_dpramxi.vhd.txt
    2.6 KB · Views: 70

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