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VHDL:Convert std_logic to integer

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christian.m

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Hey guys,

I have searched a lot to solve this simple sounding problem but haven't anything helpful yet.

Yeah i know there is a thread on this board(https://www.edaboard.com/threads/66603/) with the exact same question - but the suggested answers just don't work and **broken link removed** wasn't helpful neither!

So, how to convert a "std_logic" type to an integer - i tried four :???: different approaches but without luck :


Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

...
signal valid_vect : std_logic_vector(1 downto 0);			
signal  valid_bit : in std_logic
signal  user_select: in std_logic; -- User select
...
valid_vect(user_select)<=in_valid; -- <= "Type error near user_select; current type std_logic; expecting type natural"
valid_vect(to_integer(unsigned(user_select)))<=in_valid; -- "Cannot convert type std_logic to type unsigned"
valid_vect(to_integer(unsigned(""&user_select)))<=in_valid; -- <= does't work either : "found '4' definitions of operator "&", cannot determine excat overloaded mathich definitiion for "&" "
valid_vect(to_integer(unsigned("0"&user_select)))<=in_valid; -- <= does't work: "found '4' definitions of operator "&", cannot determine excat overloaded mathich definitiion for "&" "

What bothers me the most is that version 3&4 won't work...

Could you please help me?! Thank you so much.:sad:
 
Last edited by a moderator:

let me answer these idividually

christian.m said:
valid_vect(user_select)<=in_valid; -- <= "Type error near user_select; current type std_logic; expecting type natural"
Click to expand...

a std_logic is not an integer. hence the failure

valid_vect(to_integer(unsigned(user_select)))<=in_valid; -- "Cannot convert type std_logic to type unsigned"
Click to expand...

exactly like it says. a std_logic is not a vector, and so cannot be directly converted to an unsigned. Hence the failure.

valid_vect(to_integer(unsigned(""&user_select)))<=in_valid; -- <= does't work either : "found '4' definitions of operator "&", cannot determine excat overloaded mathich definitiion for "&" "
valid_vect(to_integer(unsigned("0"&user_select)))<=in_valid; -- <= does't work: "found '4' definitions of operator "&", cannot determine excat overloaded mathich definitiion for "&" "
Click to expand...

These 2 are the same error. The problem is that doing this:

"0" & user_select
"" & user_select

is ambiguous because there are several types that are arrays of std_logic. So the compile doesnt know whether you want a std_logic_vector, a signed or an unsigned (I cant think of the 4th one). So to fix it, you need to tell the compiler which one you mean with a qualification (the ' character)

so this should work:
valid_vect(to_integer(unsigned( std_logic_vector'(""&user_select) )))< =in_valid;

BUT
because unsigned is also an array of std_logic, you might aswell skip the std_logic_vector step and qualify it as an unsigned:

valid_vect(to_integer( unsigned'( "" & user_select) ))< =in_valid;

This is a great lesson in the symmantics of VHDL, and the strong typing system (that some people loath). But with proper coding you can avoid most of the type conversions/qualifications.

---------- Post added at 10:57 ---------- Previous post was at 10:55 ----------

The lesson here would be to have user_select as an integer rather than std_logic.
 
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    FvM

    FvM

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Your conversion attempts don't work, because std_logic is a bit while std_logic_vector is a bit vector respectively array of bits.

There are possibly other ways, but a conversion function would be the direct way:
Code: 
function sl2int (x: std_logic) return integer is
begin
  if x='1' return 1 else return 0; end if;
end;
P.S.: Thanks for reminding qualified expressions.
 

Actually go with FvMs conversion function. It's even less code :)
 

TrickyDicky said:
...
valid_vect(to_integer( unsigned'( "" & user_select) ))< =in_valid;
...
Actually go with FvMs conversion function. It's even less code :)
Click to expand...

No, your version works like hot knife through butter and gave me a deeper understanding in VHDL typecasting! Actually, I was not aware of the qualify-operator ' in VHDL.
Thanks a lot!
 

Hi All,

In the process of my code I would like tho convert the inout vector to a integer. However I try its gives 0 as output in the xilinx wave window

outline of my code:

final : inout std_logice _vecctor( 3 down to 0);
signal i : integer
process
i <=to_integer(unsigned("" & final)); I need to convert final (0010 - > 2 and store it in in i,but the value of is always a 0 !!
end process.

Please let me know my mistake
 
Last edited:

Are you sure you know how to enable input to an inout port signal? Did you cross-check with a simple input signal?

Incomplete code snippets only allow guesses...
 

one question remains with me:
what does it compile to and what is the smallest implementation, as both will do the job well.

I tend to believe that it compiles to an array of bits
 

one question remains with me:
what does it compile to and what is the smallest implementation, as both will do the job well.

I tend to believe that it compiles to an array of bits
Click to expand...
Converting std_logic_vector to integer as such changes nothing to the gate level representation of the signal. It's primarly done to fulfill specific VHDL type requirements, e.g. to use the signal as an index.
 

no, that's true, but as tricky added a '0' it changes from 1 bit to 2 bit representation, didn't it?
 

FvM said:
Are you sure you know how to enable input to an inout port signal? Did you cross-check with a simple input signal?

Incomplete code snippets only allow guesses...
Click to expand...


Unfortunately I cannot share the entire code. Its lyk 2 pages of vhdl code. All I can say is that have a decoder which generates inputs from 0 t0 15 . So the fina1 is the output of the decoder component which genrates 0 to 15 with the clock. Now all I need to convert the output to a integer and use it in a if loop for comparisions. Right now am using case statements for conversion. But I would like to know any if there is any other efficient methods available

Code: 
final : inout std_logice _vecctor( 3 down to 0);
signal i : integer
process
i <=to_integer(unsigned("" & final));   -- I need this i to give the value of binary final in integer type. But the output is always a zero
end process.
 

Unfortunately I cannot share the entire code. Its lyk 2 pages of vhdl code.
Click to expand...
That's not the point. Edaboard members can expect a complete, compilable example code that reproduces the problem, including libraries and entity port definition. I'm talking about 8 ot 10 additional lines of code.

When you assemble the example code, there are two possible results:
- the problem can be reproduced, then others can research about it without jumping into conclusions, and hopefully give you a solution.
- the problem can't be reproduced, because your assumptions about the problem are wrong. You proceeded one step in inding the solution yourself.

P.S.:
no, that's true, but as tricky added a '0' it changes from 1 bit to 2 bit representation, didn't it?
Click to expand...
A constant 0 still doesn't add logic, it's more a kind of trick to comply with the syntax or specific numeric type requirements.
 

because you didn't post a full example, I'm going to make a guess, seeing as we seem to be playing a guessing game and after a couple ales I become more suseptable to guessing games (well, at least the quiz navyhine in the pub!)

final is an inout for some silly reason so you're not driving it properly and all you get is xxxxxx, so when converted to an integer, all you ever get is 0.

- - - Updated - - -

lucbra said:
no, that's true, but as tricky added a '0' it changes from 1 bit to 2 bit representation, didn't it?
Click to expand...

iirc I converted a single std logic to an array of std_logic of length 1.
 
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