Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
In verilog language this is how synchronous & asynchronous signals are being described. Assume we have reset and clock signals
// reset is asynchronous with clock
always @ (posedge clock or negedge reset)
if (reset == 1'b1)
// then reset the circuit
else
// make the calculation with clock
In the second example there is not any dependancy between reset and clock => reset and clock are asynchronous