How to achieve this pulse timing in VHDL code

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ex00 is
    Port ( clk : in  STD_LOGIC;
              reset : in  STD_LOGIC;
           lval : out  STD_LOGIC;
           dval : out  STD_LOGIC);
end ex00;
 
architecture Behavioral of ex00 is
 
signal count_div_16 : std_logic_vector(3 downto 0);
signal count_1000   : integer range 0 to 999;
 
begin
 
clk_div_16 : process(clk, reset)
     begin
       if reset = '0' then
            count_div_16 <= (others => '0');
       elsif (clk='1' and clk'event) then
            count_div_16 <= count_div_16 + "1";
       end if;
end process; 
 
cntr_1000 : process(count_div_16(3), reset)
    begin
        if reset = '0' then 
            count_1000 <= 0;
        elsif falling_edge(count_div_16(3)) then --rising_edge???
            if count_1000 = 999 then 
                count_1000 <= 0;
            else 
                count_1000 <= count_1000 + 1;
            end if;
        end if;
end process;
 
dval <= count_div_16(3);
lval <= '1' when (0 <= count_1000 and count_1000 < 256) else '0';
 
end Behavioral;

Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY ex00_tb IS
END ex00_tb;
 
ARCHITECTURE behavior OF ex00_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ex00
    PORT(
         clk : IN  std_logic;
            reset : IN  std_logic;
         lval : OUT  std_logic;
         dval : OUT  std_logic
        );
    END COMPONENT;
    
 
   --Inputs
   signal clk : std_logic := '0';
    signal reset : std_logic := '0';
 
    --Outputs
   signal lval : std_logic;
   signal dval : std_logic;
 
   -- Clock period definitions
   constant clk_period : time := 62.5 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: ex00 PORT MAP (
          clk => clk,
             reset => reset,
          lval => lval,
          dval => dval
        );
 
   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;
 
 
   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
      wait for 100 ns;  
        reset <= '1';
 
      wait for clk_period*10;
 
      -- insert stimulus here 
 
      wait;
   end process;
 
END;