In most schemes on SPI I've seen no resistors at all are present. I've been thinking about this and made these observations. Please tell me what you think.

1 / When sharing 2 slaves on one SPI bus with a PIC being master, during the PIC reset stage its CS* outputs are still tri-stated. Noise could made the 2 slaves at the same time believe they are selected and they could start broadcasting => short circuit on the MISO line killing the mcu port or any of the slaves. => pull-up resistor on all CS* lines.

2 / When analysing SPI communication diagrams, the slaves have their outputs tri-stated also whenever they are not supposed to send out something useful. With the PIC MISO configured as input, it sits part of its time listening to a floating input leading to switching consumption caused by noise => pull up/down on MISO line.

Is this exaggerated thinking or what do you think?