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Here there is an article on wafer calibration (Test Structures and Techniques for On-Wafer CMOS TRL Calibration
Michael Bohl Jenner and Troels Emil Kolding) and a technical report (Technical report R97-1006
ISSN 0908-1224
On-Wafer 3-port S-parameter Calibration
October 1997
Michael B. Jenner
M.Sc.E.E
Department of Communication Technology
Institute of Electronic Systems
Aalborg University
Frederik Bajers Vej 7A, DK-9220 Aalborg East, Denmark)
I hope it can help.
Mazz
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