Verilog issue using Quartus II

Hello,

I'm targetting Cyclone IVE using the Quartus II synthesis tool. I have the following problem:

I have a section of code which is going to be repeated dozens of times in my code. It is effectively a state machine which executes a number of statements sequentially on the posedge of a clock. My first thought was to put the code in a task and instantiate it multiple times in the code. However, my understanding is that this is not possible because the code uses a clock and you can only pas values at one moment in time to a task, not a changing clock signal.

My second thought was to place the code in a seperate module and use a generate conditional statement to instantiate it. The problem with this approach is that the chip selects that determine which values are to be sent to the module are not available at elaboration time: they will be sent by the host processor during run time. My understanding is that the generate statement works at elaboration time only.

My third thought was to use if statements within an "always @ posedge (clock)" construct to monitor the chipselects and then pass the appropriate values to the module in an instantiation call. I've read however that it is not permissable to call a module from within an always statement.

Are my assumptions above correct? Does anyone know any other way of doing this?

best regards,

John

It's not quite clear what you mean with chip selects respectively, what's the variable part in the generated module instantiations. Can you clarify this with an example?

I presume, that the function of the individual state machines is well defined and the problem is only about a suitable way to avoid duplicated text writing.

Thanks for the response.

Yes - the issue is to avoid writing out hundreds of lines of code where the same state machine is used a number of times but with different values passed to it.

Ref chip selects, these are used to select which mode of operation I am running a sensor chip in and they therefore determine the parameters that I pass to the state machine. The chipselects are passed to the FPGA on the host processor bus as an address and correseponding read or write enable depending on the operation to be performed by the sensor.

So, the logical process I'm trying to follow is

if (chipselect_1)
execute the state machine with parameter_set_1

if (chipselect_2)
execute the state machine with parameter_set_2

etc etc

I think I have figured out a way to solve the probelm by hosting the state machine in a seperate module but instead of trying to initiate the state machine from the main module, I pass all the chipselects to the state machine module and generate the appropriate parameter set within the second module. As mentioned in the previous mail, my first thoughts had been to determine the mode of operation from within an if - else statement in the main module and call the state machine from there which seems to be impossible.

I'm hoping to simulate this today - I'll let you know how I get on.

Thanks again,

John

As a possible solution to determine the behaviour at run time, you could e.g. write operation parameters to the individual state machine instances through a bus interface. Different interface adresses can be implemented as a generate parameter. In so far, I think your plans are generally feasible. Of course, limited FPGA resources may be a problem.

You can do some thing like this,

1. One instance of your code.
2. Design decoder circuit for chipselect and other signals, since only once chipselect will active at a time this will work.
3. To optimize mux and decoder logic you can use generate statement with if..else construct. (This is optional. will result in optimized hardware resource)

HTH,
Shitansh Vaghela