I working on some application that gonna be implement on FPGA
It involve with sample signal by 512 over sampling ratio and then decimate the signal by this OR - 512 (DELTA SIGMA MODULATION)
does some one have a good idea for me about the decimation filter block
i thought about 3 options-

1 - CIC DECIMATE BY 128 AND THEN INVERS SINC TO COMPENSATE (fir2 in matlab) and then 2 fir that each of them decimate by 2

2 - polyphase decimators .

3 - use simulink blocks - first CIC DECIMATION then CIC COMPENSATION and then FIR DECIMATION

I will be vwry happy to another ideas that would be applicatiable for FPGA