Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] LVS error: ERC Pathck polygons

Status
Not open for further replies.
A

allennlowaton

Full Member level 5
Joined
Oct 5, 2009
Messages
247
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Location
Taiwan
Activity points
3,062
Hello EDA fellows,

Lately, I've been doing LVS with my layout.
Although, the LVS's Comparison Result is good (green smiley is ON), there's
still one problem, the ERC pathchk polygons.
I hope anyone can shed light on how to debug them.

 

I just checked the connections. The problem was solved already.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top