10-bit SAR ADC, Unit-Cap size, Poly-Poly Caps

For a 10-bit SAR ADC with binary-weighted Capacitive DAC, what should be a good unit-size? Note that the process can only support Poly-Poly caps so bottom plate parasitics are going to quite high, I've read somewhere that they can be as high as 30%.

I am looking for 9+ ENOB. Die area is not a big concern, even speed is under 5 KSPS. Was thinking of simply using a single slope ADC but for 10-bit, the clock will be around 5MHz, maybe too noisy for other sensitive very low noise circuits on the die. Also thought of a Sigma-Delta(first order) but base-band extends to DC and I haven't implemented one, especially with dithering before). Any suggestions? I am open to new architectures within reasonable power and mostly low noise to other circuits that detect Sub-uV range signals.

For speed below <10KSPS sigma-gelta ADC is about standard. It provide reliable in noisy environment, accurate and flexible solution, - tardeoff between Resolution/Speed is achieved by digital harware modification only. Best to use 2-nd order SDM & 3-d order decimation filter, but if you have big margin of oversampling ratio for 10-bit accuracy a 2-nd order decimator can be also allowable.

For 10-bit resolution, 20umx20um to 25umx25um should be fine.