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Comparator design Help !!

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khabib

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This is the first time that I am going to design an comparator and very new to analog design.
1. What do I need to simulate for comparator as for opamp, we usually do open loop gain,
slew rate, PSRR, CMRR etc.

2. How to choose the device geometry ? For opamp it is like for matching and other minimum L is 3/4 times higer than the allowable minimum length of the transistor.

3. application of this comparator will be in a cyclic A/D.

Any other help/tips will be appreciated.

Thanks,

Khabib
 

1. measure the open loop gain. the most important parameter is the input offset voltage. check on these two.
2.as a rule of thumb, the length of the mos is 2-5 times bigger than the min length. for the width, consider the matching and the current mirror.
 

A reminder, for a comparator, speed may be a issue to be considered.
 

**broken link removed**
 

micel99 said:
A reminder, for a comparator, speed may be a issue to be considered.
Click to expand...

yes, speed is one of the most important factors of comparator, and the other is offset.
both open loop gain and opamp bandwidth contribute to speed.
i have no idea of comparators in cyclic adc. but if a comparator used in a pipeline adc, speed is everything provided that the stage resolution is not high. you may add a pre-amp stage to improve the comparator speed, at the same time, kickback noise is reduced due to the pre-amp.
 

Hey totoro,

By the way, what is it called kickback? When does it appear? What's its cause?

Thank you
 

Hi

Kickback noise is due to the switching of the transistors.

I think you can refer John and Martin Book.

Suraj
 

Humungus said:
Hey totoro,

By the way, what is it called kickback? When does it appear? What's its cause?

Thank you
Click to expand...

The decision circuit of a voltage comparator uses positive feedback to
increase the gain of the decision element. The switch noise coming from the positive feedback
stage will corrupt the input of the comparator and often limit its performance in the actual circuit.
In the sample-and-hold circuit, if the kickback noise is not isolated, it will
feed directly into the input voltage of the op-amp in S/H circuit through the input capacitor, and drastically affect the output of the sample-and-hold.
 

Dear:
The speed and the gain of the comparator is the imporatnt issues.
U should find out the spped and the gain of the comparator used in your sub-system.
The first stage of the comparator should used mini Cgs to reduce the kick-back noise. And the output of the dc operating point should be cared.
Finally, the final stage differetial to single-end dc operating point should be about Vdd/2 to get good 50-50 duty.
 

**broken link removed** - link in not working, can u pls check. Thanks!!
 

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