Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

tiny encryption algorithm

Status
Not open for further replies.
F

frank90

Newbie level 3
Joined
Sep 29, 2011
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,299
currently i writing a TEA using VHDL. however i facing problem with the output that i get from simulation, hoping that someone can help me with it. your help is really appreciated!
 

Attachments

  • Capture.JPG
    Capture.JPG
    130.6 KB · Views: 79
Last edited:

remove modereg,input0,input1 from the sensitivity list.

but otherwise whats the problem?
 

the problem is that why there are so many output. it seems like it keep looping inside the process.
 

it seems like it keep looping inside the process.
Click to expand...
It's not "looping". Some signals are added up each clock cycle, as your code commands.

I guess, it's time to think about a specification of intended behaviour.
 

then if i want to get the only one correct output, how should i modify the code. thanks for the help.
 

I'm not familiar with the algorithm, but I guess, it involves a well defined number of "rounds". You'll obviously need a start signal, a round counter and a ready output that signals end of conversion. The "correct output" may be stored in an output register.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top