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    Multiply and Accumulate Architectures for FIR and IIR filters

    Hi All,

    Has anyone done the survey on MAC architectures for digital filters in terms of performance, power consumption, less chip area? I want the details that how much work has been done on it. If yes , can you please provide the details/report of that?

    Thanks alot,

    Regards,
    Naveed

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    Re: Multiply and Accumulate Architectures for FIR and IIR filters

    Current Processors can compute 1 output per cycle for a 10 tap FIR filter, may take 3-4 cycles per 1 output for a 10 tap IIR filter.
    Hope that helps........



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  3. #3
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    Re: Multiply and Accumulate Architectures for FIR and IIR filters

    Thanks for the reply chitturi,

    Can you give the name/number of the processor which you are referring to (10 point FIR in 1 cycle , 10 point IIR in 3-4 cycles). If you have some documents on survey on it , can you provide the documents too?

    Thanks & Regards,
    Naveed



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  4. #4
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    Re: Multiply and Accumulate Architectures for FIR and IIR filters

    can check below link on C64x processor. There r other later version of processors from TI.
    http://www.ti.com/lit/an/spra884a/spra884a.pdf

    Also can look at ARM Cortex-A8/A9 processors



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    Re: Multiply and Accumulate Architectures for FIR and IIR filters

    chitturi,

    Thanks chitturi; The link mentioned by you is good which has assembly optimized libraries for FIR,IIR & FFT. But it doesnt have FIR,IIR in hardware :)

    Regards,
    Naveed



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  6. #6
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    Re: Multiply and Accumulate Architectures for FIR and IIR filters

    Hi Naveed,

    I miss-understood your question. Thought you r looking for software based FIR/IIR.
    I do not know much on the hardware implementations of it.

    -suresh



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