HI ALL

i am working now on some delta sigma application - i overasample the digital input signal by 512 then pass it through delta sigma modulator and then i need to decimate it (by 512)

because i need to implement it on FPGA i thought to use CIC DECIMATION FILTERS to decimate by 256 and then use fir to decimate by 2 and to get linear phase response.

i build up some generic matlab code to this design but from some how i cant reach a good frequency response
another option is to decimate by factor 64 with cic and then use 3 more fir decimation.
my sample rate is 1e6 HZ
and the pass-band freq is 300-1e3 HZ

i will be very to get any interesting idea from u guys

thank you all