Test Bench for CIC decimation(5) filter

Can any one write a test bench to test this CIC filter...

basically i'm passing 3 sine waves of frequencies 8 MHz , 16MHz and 24 MHz in 3 separate cases with 80 MHz sine wave being the sampling signal.
I've to take 10 samples , 5 samples and 3.33 samples respectively for each of above cases. below is the excel conversion of a sine wave taking 10 samples at equal duration (i.e 2*pi / 10 = 360 degrees / 10 = 36 degrees duration)... i.e, at 36 degree, 72 degree,108 degree....360 degree.

test bench shall have a text io directive to read 18 bit data input from a text file and to write output to another text file.
using text IO is OK, but i just need a test bench , at least with out text IO directives.

Can any one help ?


decimation factor is 5.




36 0.628318531 0.58778525229247300000 77042.1885884790000 010010110011110010
72 1.256637061 0.95105651629515400000 124656.8797038380000 011110011011110000
108 1.884955592 0.95105651629515400000 124656.8797038380000 011110011011110000
144 2.513274123 0.58778525229247300000 77042.1885884791000 010010110011110010
180 3.141592654 0.00000000000000012251 0.0000000000161 000000000000000000
216 3.769911184 -0.58778525229247300000 -77042.1885884790000 101101001100001110
252 4.398229715 -0.95105651629515400000 -124656.8797038380000 100001100100010000
288 5.026548246 -0.95105651629515400000 -124656.8797038380000 100001100100010000
324 5.654866776 -0.58778525229247300000 -77042.1885884791000 101101001100001110
360 6.283185307 -0.00000000000000024503 -0.0000000000321 000000000000000000




-- Module Name: cic.vhd
-- Target Devices: XC6VSX315t-1ff1156
-- Tool versions: ISE 12.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity cic is
generic(CI_SIZE : integer := 18; -- cic input data width
CO_SIZE : integer := 30; -- cic output data width
STAGES : integer := 5);
ce : in std_logic; -- clock enableport (clk : in std_logic; -- system clock (80 Mhz)

ce_r : in std_logic; -- decimated clock by factor of 5 used in comb section
rst : in std_logic; -- system reset
d : in std_logic_vector (CI_SIZE-1 downto 0); --input data
q : out std_logic_vector (CO_SIZE-1 downto 0)); --output data
end cic;

architecture syn of cic is
-- array definition for integrator and comb section
type d_array_type is array (STAGES downto 0) of std_logic_vector(CO_SIZE-1 downto 0);
-- array definition for comb section
type array_type is array (STAGES downto 1) of std_logic_vector(CO_SIZE-1 downto 0);

signal d_fs : d_array_type;
-- used in the integrator section
signal d_fsr : d_array_type;
-- used in the differentiator section, at rate r
signal m1 : array_type;
-- used in the differentiator section, at rate r
signal id : std_logic_vector(CO_SIZE-1 downto 0):= (others =>'0');
-- to use for sign extended version of the input


begin
-- output data
q <= d_fsr(STAGES);
-- input data (d input is sign extended to 30 bits)
id(CO_SIZE-1 downto CI_SIZE) <= (others => d(CI_SIZE-1));
id(CI_SIZE-1 downto 0) <= d;
-- integrator section
process(clk)
begin

if(clk'event and clk = '1') then
if(rst = '1') then
d_fs(0) <= (others => '0');
for i in 1 to STAGES loop
d_fs(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fs(0) <= id;
for i in 1 to STAGES loop
d_fs(i) <= d_fs(i-1) + d_fs(i);
end loop;
end if;
end if;
end process;

-- differentiator (comb) section
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
d_fsr(0) <= (others => '0');
for i in 1 to STAGES loop
m1(i) <= (others => '0');
d_fsr(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fsr(0) <= d_fs(STAGES);
if (ce_r = '1') then
for i in 1 to STAGES loop
m1(i) <= d_fsr(i-1);
d_fsr(i) <= d_fsr(i-1) - m1(i);
end loop;
else
m1 <= m1;
for i in 1 to STAGES loop
d_fsr(i) <= d_fsr(i);
end loop;
end if;
end if;
end if;
end process;
end syn;

we cant write a testbench for you. - do you have any specific questions?

Why do you want text_io to read in a sine from a text file? Generating a sine is one line of code in the test bench.

- generate the reset signal
- generate clk and ce_r by processes with wait statements
- generate the input signal using ieee.math_real functions

I have written following test bench, but getting syntax error while simulating this code...
can anyone help me in correcting this code.. (functional part mainly)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use std.textio.all;
use ieee.std_logic_textio.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY CICTEST IS
END CICTEST;

ARCHITECTURE behavior OF CICTEST IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT cic
PORT(
clk : IN std_logic;
ce : IN std_logic;
ce_r : IN std_logic;
rst : IN std_logic;
d : IN std_logic_vector(17 downto 0);
q : OUT std_logic_vector(29 downto 0)
);
END COMPONENT;


--Inputs
signal clk : std_logic := '0';
signal ce : std_logic := '0';
signal ce_r : std_logic := '0';
signal rst : std_logic := '0';
signal d : std_logic_vector(17 downto 0) := (others => '0');

--Outputs
signal q : std_logic_vector(29 downto 0);

file in_file:text is in "cic_in.txt";
variable inline: line;


-- Clock period definitions
constant clk_period : time := 50 ns;


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: cic PORT MAP (
clk => clk,
ce => ce,
ce_r => ce_r,
rst => rst,
d => d,
q => q
);

-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;


-- reset process
reset: process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*10000000;
end process;


-- clk enable process
cenable: process
begin
ce <= '1';
wait;
end process;

-- decimated clk process
cenable_r: process
begin
ce_r <= '0';
wait for clk_period*5;
ce_r <= '1';
wait for clk_period;
end process;


-- generating i/p file

ip: process (clk)
file in_file:text is in "cic_in.txt";
variable inline: line;
variable in_tmp: std_logic_vector(17 downto 0);
begin
if(clk'event and clk='1') then
if not endfile(in_file)then
readline(in_file,inline);
read(inline,in_tmp);
d <= in_tmp;
end if;
end process;
---------------------

-- generating o/p file

op: process (clk)
file file_out:text is out "cic_out.txt";
variable line_out : line;
variable output_tmp : std_logic_vector(29 downto 0);
begin
if(clk'event and clk='1') then
output_tmp := q;
write(line_out, output_tmp);
writeline(file_out,line_out);
end if;
end process;
---------------------

How about revealing the error messages and marking the error locations?

There's at least a missíng end if in the input file read process.

ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic/cic.vhd" Line 12: Syntax error near "ce".
ERROR:HDLCompiler:854 - "E:/lab_fpga/lab3/cic/cic.vhd" Line 8: Unit <cic> ignored due to previous errors.
ERROR:HDLCompiler:854 - "E:/lab_fpga/lab3/cic/cic.vhd" Line 20: Unit <syn> ignored due to previous errors.

---------- Post added at 22:19 ---------- Previous post was at 22:16 ----------

ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic/cic.vhd" Line 12: Syntax error near "ce".
ERROR:HDLCompiler:854 - "E:/lab_fpga/lab3/cic/cic.vhd" Line 8: Unit <cic> ignored due to previous errors.
ERROR:HDLCompiler:854 - "E:/lab_fpga/lab3/cic/cic.vhd" Line 20: Unit <syn> ignored due to previous errors.

these are the error messages....besides these i'm not quite sure if we have to include some directives to open files..

---------- Post added at 22:24 ---------- Previous post was at 22:19 ----------

010010110011110010
011110011011110000
011110011011110000
010010110011110010
000000000000000000
101101001100001110
100001100100010000
100001100100010000
101101001100001110
000000000000000000
these inputs should be feed to the cic filter..

Read the error messages more thoroughly. The syntax error is in the component code, not the test bench.

fOLLOWING are the errors i'm getting now...

now cic.vhd functional code is proper without errors....
but test bench has some errors..
can you pls help now ?

------------------------------------------------------------------------------------------------------------------------------------------



ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 139: Syntax error near "process".
ERROR:HDLCompiler:837 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 145: Type void does not match with a string literal
ERROR:HDLCompiler:1728 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 146: Type error near line ; current type line; expected type void
ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 147: Syntax error near "variable".
ERROR:HDLCompiler:620 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 147: Near std_logic_vector ; type conversion does not match type void
ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 148: Syntax error near "begin".
ERROR:HDLCompiler:62 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 150: output_tmp is not a variable
ERROR:HDLCompiler:841 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 152: Expecting type text for <file_out>.
ERROR:HDLCompiler:187 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 152: Actual file_out of formal f must be a file
ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 145: Syntax error near "file".r "process".
ERROR:HDLCompiler:806 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 154: Syntax error nea




--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:29 09/26/2011
-- Design Name:
-- Module Name: Z:/lab3/CICTEST.vhd
-- Project Name: lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use std.textio.all;
use ieee.std_logic_textio.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY CICTEST IS
END CICTEST;

ARCHITECTURE behavior OF CICTEST IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT cic
PORT(
clk : IN std_logic;
ce : IN std_logic;
ce_r : IN std_logic;
rst : IN std_logic;
d : IN std_logic_vector(17 downto 0);
q : OUT std_logic_vector(29 downto 0)
);
END COMPONENT;


--Inputs
signal clk : std_logic := '0';
signal ce : std_logic := '0';
signal ce_r : std_logic := '0';
signal rst : std_logic := '0';
signal d : std_logic_vector(17 downto 0) := (others => '0');

--Outputs
signal q : std_logic_vector(29 downto 0);

file in_file:text is in "cic_in.txt";
variable inline: line;


-- Clock period definitions
constant clk_period : time := 12.5 ns;


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: cic PORT MAP (
clk => clk,
ce => ce,
ce_r => ce_r,
rst => rst,
d => d,
q => q
);

-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;


-- reset process
reset: process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*10000000;
end process;


-- clk enable process
cenable: process
begin
ce <= '1';
wait;
end process;

-- decimated clk process
cenable_r: process
begin
ce_r <= '0';
wait for clk_period*5;
ce_r <= '1';
wait for clk_period;
end process;


-- generating i/p file

ip: process (clk)
file in_file:text is in "cic_in.txt";
variable inline: line;
variable in_tmp: std_logic_vector(17 downto 0);
begin
if(clk'event and clk='1') then
if not endfile(in_file)then
readline(in_file,inline);
read(inline,in_tmp);
d <= in_tmp;
end if;
end process;
---------------------

-- generating o/p file

op: process (clk)
file file_out:text is out "cic_out.txt";
variable line_out : line;
variable output_tmp : std_logic_vector(29 downto 0);
begin
if(clk'event and clk='1') then
output_tmp := q;
write(line_out, output_tmp);
writeline(file_out,line_out);
end if;
end process;
---------------------
END;














FUNCTIONAL CODE.................................................................


-- Module Name: cic.vhd
-- Target Devices: XC6VSX315t-1ff1156
-- Tool versions: ISE 12.2
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity cic is
generic(CI_SIZE : integer := 18; -- cic input data width
CO_SIZE : integer := 30; -- cic output data width
STAGES : integer := 5);
port (clk : in std_logic; -- system clock (80 Mhz)
ce : in std_logic; -- clock enable
ce_r : in std_logic; -- decimated clock by factor of 5 used in comb section
rst : in std_logic; -- system reset
d : in std_logic_vector (CI_SIZE-1 downto 0); --input data
q : out std_logic_vector (CO_SIZE-1 downto 0)); --output data
end cic;

architecture syn of cic is
-- array definition for integrator and comb section
type d_array_type is array (STAGES downto 0) of std_logic_vector(CO_SIZE-1 downto 0);
-- array definition for comb section
type array_type is array (STAGES downto 1) of std_logic_vector(CO_SIZE-1 downto 0);

signal d_fs : d_array_type;
-- used in the integrator section
signal d_fsr : d_array_type;
-- used in the differentiator section, at rate r
signal m1 : array_type;
-- used in the differentiator section, at rate r
signal id : std_logic_vector(CO_SIZE-1 downto 0):= (others =>'0');
-- to use for sign extended version of the input


begin
-- output data
q <= d_fsr(STAGES);
-- input data (d input is sign extended to 30 bits)
id(CO_SIZE-1 downto CI_SIZE) <= (others => d(CI_SIZE-1));
id(CI_SIZE-1 downto 0) <= d;
-- integrator section
process(clk)
begin

if(clk'event and clk = '1') then
if(rst = '1') then
d_fs(0) <= (others => '0');
for i in 1 to STAGES loop
d_fs(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fs(0) <= id;
for i in 1 to STAGES loop
d_fs(i) <= d_fs(i-1) + d_fs(i);
end loop;
end if;
end if;
end process;

-- differentiator (comb) section
process(clk)
begin
if(clk'event and clk = '1') then
if(rst = '1') then
d_fsr(0) <= (others => '0');
for i in 1 to STAGES loop
m1(i) <= (others => '0');
d_fsr(i) <= (others => '0');
end loop;
elsif(ce = '1') then
d_fsr(0) <= d_fs(STAGES);
if (ce_r = '1') then
for i in 1 to STAGES loop
m1(i) <= d_fsr(i-1);
d_fsr(i) <= d_fsr(i-1) - m1(i);
end loop;
else
m1 <= m1;
for i in 1 to STAGES loop
d_fsr(i) <= d_fsr(i);
end loop;
end if;
end if;
end if;
end process;
end syn;

---------- Post added at 16:51 ---------- Previous post was at 16:48 ----------

This is what i have to do....

Generate the free running clock, reset for one cycle and ce_r (decimated clock that generates
one clock pulse for every 5 clock cycles). Clock enable (ce) can be tied to logic 1 so the filter
is always enabled).
3. Testing at 8 MHz passband: In this region, the filter is supposed to pass the sine wave with
some change on magnitude. Apply an 8 MHz sine wave sampled by 80 MHz. This means
you need 10 samples, each one applied at a 80 MHz clock and it is repeating. Read the input
data samples from a file using TEXT IO and apply the input to the design. Read the output
values from the waveform and draw both of the waveforms on the same graph.

---------- Post added at 16:56 ---------- Previous post was at 16:51 ----------

----------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
below are the 10 samples of 8 MHz wave taken at equal sine angles of 36 degrees and normalised...i.e, multiplied by 2^17 (input data width 0:17) and then converted to signed binary number..

010010110011110010
011110011011110000
011110011011110000
010010110011110010
000000000000000000
101101001100001110
100001100100010000
100001100100010000
101101001100001110
000000000000000000
these inputs should be feed to the cic filter..

Right:

at line 139, you're missing an end if.

and for the rest - you are using '87 file usage. I wouldnt recommended. I would use this format which is '93 format:

file in_file : text open read_mode is "cic_in.txt";

and the same for all the other files.

Another thing - please please please use code tags in your posts.

Each error message comes with a line number. Locating the respective line is the first step to identify the error cause.

I'm under the impression, that you didn't yet take the effort. Why should we?

I somehow managed to clear most errors.. except one at line 8 of this code in test bench...( i.e, at line readline(in_file,temp); ) and the error message isERROR:HDLCompiler:1728 - "E:/lab_fpga/lab3/cic_work/tb_cic.vhd" Line 140: Type error near in_file ; current type line_file; expected type text

I'm just started learning VHDL for my FPGA lab.. this is my first lab...so, not that acquainted with syntax of VHDL and using its functions...
can any1 help me in figuring out what needs to e corrected ?


read_input: process(clk)
type line_file is file of std_logic_vector;
file in_file: line_file;
variable temp: std_logic_vector (17 downto 0 );
begin
file_open(in_file, "cic_in.txt", READ_MODE);
while not endfile(in_file) loop
readline(in_file, temp);
d <=temp;
end loop;
file_close(in_file);
end process;

the problem is you defined your own file type. if you define your own file type, you will have to define your own read functions.

If you stick with the text file type (from textio) then all the read functions are defined for you.

And you still havent found the code tags? use code and /code inside square brackets [ ]

Hi TrickyDicky,

Can you please explain in detail. I dint get your point of defining "own file type". I am also new to VHDL. So need help.

Regards
Vinod A H

type line_file is file of std_logic_vector;

with this line you have declared a file of std_logic_vector.
because it is not a standard file type (because you created it) there are no readline functions for it - you have to write your own. you can however use read(file, slv) to read directly to a std_logic_vector (because read is implicitly declared for all file types). But the bahaviour is not garanteed (plus it becomes a data file, not a text file)

the only "standard" way to read files is to use the "text" file type, that is declared in the textio library. and there are loads of read functions written for that.