Doubts on internal Power from PTPX Power Reports

I used two VCD files from a design to run PTPX to generate power reports.
One VCD file was obtained using netlist simulation without SDF annotation while the other one was with SDF.
PTPX was run in both averaged and time_based modes.

The reports were showing that the total internal power from VCD without SDF was more than double of that from VCD with SDF.
The sequential logics were having the same phenomenon, but the internal power of combinational logics was almost the same for VCD with SDF and VCD without SDF.

The situation existed in reports from averaged and time_based mode as well.

Please kindly leave your comments and suggestions.
Thanks.

---------- Post added at 17:54 ---------- Previous post was at 17:06 ----------

Another doubt is about peak power.
The peak power without SDF is much less than that with SDF.

From my understanding, the peak power with SDF should be less because delays are inserted so the power is sort of being averaged out.
Please point out my mistakes.
Thank you.

Slaam
Have you found out the reason yet?

The reason for this difference is
With sdf there can be glitches and combo logic gates will react to thos glitch and consume power.
Without sdf every thing is delta delay so no gltiches and you see less power.

Same concept will apply for peak power also.