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verilog interview question

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ADITYAVARDHAN

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Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin
a = 0;
a <= 1;
$display(a);
end


Please answer the question with reason.
Thank you
 

The answer to this question is :

# 0
# 0

This is because of the first blocking assignment to a. This will block the 2nd non-blocking assignment till it assigns and prints the value of a=0. So you will get only 0,0 .
Try this code in Modelsim or anyother simulator and see.
 

This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue.
Only events in the active queue are completed this simulation cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next simulation cycle, it would show 1.
 

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