Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
difference between FPGA and ASIC is very big, both of them do implement integrated circuits but the cost/volume of ASIC is cheaper than FPGA which is viable only for low volume production. As for the techonological differences, ASIc performance far exceed that of an FPGA speed and density wise. ASIc can be customized more effeciently than FPGA.
for I/O cells tyou instantiate them from within DC or you are doind custom design then can call them for a cell library
Thank you!
Now I also have same questions:
1.at ASIC, how to temp with the interior data bus,with MUX-selector or Three-state-bus?
2.,how to set accordingly variable of DC constraints to terminate the "assign" definition at the netlist after DC
General Differences are,
1) TimeToMarket for ASIC is more.
2) We can achieve less i/o delay with ASIC.
3) FPGA time to market is less.
4) FPGA has fixed i/o delay.
1) There is no difference between codes for FPGA and ASIC. Really no difference. :?
2) You must instantiate an IO pad from the pad library using "port map" statement in VHDL and simple "io_pad u_io_pad_0(.I(), .O())" in Verilog.
In ASIC you have 3 diferent developments alternatives:
Custom : where you have a completly control in your design. It is expensive and requires a large development type.
Semicustom : here you must consider somo especificatoon from the producer .
Programable: you must take the consideration of the chip that you are programing, here you can use FPGA.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
