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metal widths for the interconnection and routing of the powerMOSes

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allennlowaton

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Hello EDA fellows,
I would like to ask for your help regarding the required or allowable metal widths for the routing of the powerMOSes during
the layout. The devices has 20000um for the widths.
Shown below is the circuit for my charge pump.
The current expected at the output is 80mA.

 

allennlowaton said:
The current expected at the output is 80mA.
Click to expand...

Without knowing your process, here's a rule-of-thumb: Use 1µm/mA [width/current] for commercial/industrial chips (i.e. up to 85°C op.temp.), about twice this value for mil. applications (op.temp. up to 125°C). If possible, you may distribute the resultant width on more than 1 metal layer. Top metal layers often are thicker and so might need just half of such required width.

In sub-micron processes you'll have to take care of slicing wide wires.
 
erikl;953338. If possible said:
this one is not clear to me though. hope you can expound this one for me.
I'm using the 0.35um 5V process
thank you erikl..
Click to expand...
 
Last edited:

erikl said:
If possible, you may distribute the resultant width on more than 1 metal layer.
Click to expand...
allennlowaton said:
this one is not clear to me
Click to expand...

Instead of using 1 metal layer of 80µm width, you could use two 40µm wide metal layers over each other, connected by a via chain. Or 4 metal layers of 20µm widths. If available, use the thick top metal layer.

Then don't use too many vias in between, in order not to block the longitudinal current flow too much.
 
mA/um depends on the layer thickness. You won't go wrong with a 1E5 A/cm2
current density I/(t*w). Beware the via current density, via sidewall can often
be a weak point. Any foundry PDK ought to give you reliability rules of this sort.
 
Typical VIA current density is 1mA/VIA
 

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