Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to find latency of input to output in SoC Encounter

Status
Not open for further replies.

lien0205

Newbie level 5
Joined
Dec 3, 2009
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,345
Hi guys,

I am a newbie in SoC Encounter but I need to figure out how many clock cycles for my chip to finish one calculation. So do u know if I could get this clock cycles from SoC Encounter by using any command or method?

Thank you.

Best,

Lien
 

Hi guys,

I am a newbie in SoC Encounter but I need to figure out how many clock cycles for my chip to finish one calculation. So do u know if I could get this clock cycles from SoC Encounter by using any command or method?

Thank you.

Best,

Lien

Interesting question, If I understand correctly, you are writing RTL and want to figure out how many cycles you must wait until your result is ready?
I haven't written RTL myself but from rational thinking, I think, you could give the entire calculation in one clock cycle and give it to the synthesis tool.
With whatever clock you are driving this logic, you may get a negative slack on this path.
Look at the negative slack and figure out how many clock cycles it needs.

Example-
So Lets say if using a 5ns clock, you see negative slack of 9ns. Then, 9ns+5ns, the datapath would be 14ns. With a 5ns clock, you need 3 clock cycles.

If there is a better way, somebody can correct me.

Thanks,
 

Interesting question, If I understand correctly, you are writing RTL and want to figure out how many cycles you must wait until your result is ready?
I haven't written RTL myself but from rational thinking, I think, you could give the entire calculation in one clock cycle and give it to the synthesis tool.
With whatever clock you are driving this logic, you may get a negative slack on this path.
Look at the negative slack and figure out how many clock cycles it needs.

Example-
So Lets say if using a 5ns clock, you see negative slack of 9ns. Then, 9ns+5ns, the datapath would be 14ns. With a 5ns clock, you need 3 clock cycles.

If there is a better way, somebody can correct me.

Thanks,

Thank you huckle. But what if my negtive slack is possitive? Say using 5ns clock and worst negative slack is 0.5ns. Does it mean I only need 5-0.5 ns to finish my calculation?

Lien
 

Thank you huckle. But what if my negtive slack is possitive? Say using 5ns clock and worst negative slack is 0.5ns. Does it mean I only need 5-0.5 ns to finish my calculation?

Lien

Yes, then you only need 4.5ns for the path, that means one clock cycle is good.
 

Yes, then you only need 4.5ns for the path, that means one clock cycle is good.

But the problem is I don't know how to find the total negtive slack in my chip. The only thing I could get is the worst negtive slack and how many total paths as shown below:

+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.109 | 0.109 | 1.000 | 0.414 | 0.297 | N/A |
| TNS (ns): | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | 0 | N/A |
| All Paths:|3.16e+05 |3.15e+05 | 789 | 242 | 64 | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+

So do u know how could I get this total negtive slack number?

Thank you.

Lien
 

But the problem is I don't know how to find the total negtive slack in my chip. The only thing I could get is the worst negtive slack and how many total paths as shown below:

+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
| WNS (ns):| 0.109 | 0.109 | 1.000 | 0.414 | 0.297 | N/A |
| TNS (ns): | 0.000 | 0.000 | 0.000 | 0.000 | 0.000 | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | 0 | N/A |
| All Paths:|3.16e+05 |3.15e+05 | 789 | 242 | 64 | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+

So do u know how could I get this total negtive slack number?

Thank you.

Lien


You have no violating paths, which means you meet setup timing.
Total negative slack would only be anything else than zero if you had failing paths.

Hope this helps,
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top