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Closed loop bandwidth simulation of MDAC for Pipeline ADC

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mischivis

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I'm having trouble setting up an AC simulation of an MDAC for a Pipeline ADC. This is a switched
capacitor circuit so it can be in either Sample or Hold mode. Do I perform an AC simulation
in Hold mode of operation? What does the 3 dB bandwidth need to be?
 

In sample mode you just sample the input and reset the amplifier. In hold mode you close the feedback. So, if I understand you question correctly, you should test your MDAC in hold mode. The 3db BW is closely linked to the settling time you're targeting.
 

What I'm trying to do is perform an AC simulation of the MDAC in hold mode, when the loop is closed. Theoretically, I
should see a DC gain of (Cf+Cs)/Cf = 2 if Cs=Cf. How do I setup this simulation? Where do I put the AC source?
 

one way would be to put the ac source at that end of Cs that's not connected to the input of the amplifier. To get meaningful results though, you need to have the right operating point. I think you have two options. First, simulate it in transient and save the operating point at the end of the hold phase, just before it ends. Then force that operating point for the ac analysis. The other option is to do PAC simulation at the end of the hold phase again.
 

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