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That is the goal. But in reality buffers and inverter rarely have the same rise and fall time as it depends on the capacitive load of the clock tree its driving and the drive strength of the CLKBUF/CLKINV. So instead of of using buffers/inverters with the same rise and fall time. CTS tries to balance the load and driver to try to keep it within some parameter (usually know as CTS SKEW). It does this by driving larger clock trees with stronger CLKBUFs/CLKINVs
narfnarf
In order to maintain the duty cycle, you need to ensure that both rise and fall edges have similar transitions (if possible same transitions). And as narfnarf mentioned.. "instead of of using buffers/inverters with the same rise and fall time. CTS tries to balance the load and driver.."
Also during CTS, we also specify the Max Transitition limit for clock buffers and at flops. So, CTS tries to see that the transitions at all clock buffers & flops is almost similar and thereby we can maintain the uniform duty cycle.
We do not use normal buffers and inverted in clock-tree building!Are you saying here that the normal buffers and inverters are used in CTS also ?
the special buf/inv for clock tree are indeed special balance cells which have similar up and down transition time.
You can use normal buf/inv in clock tree if you would like to. Sometimes it is beneficial as normal buf/inv have less area and power overhead (of course if using normal cell can satify the timing constraints).
Which cell can be used in clock tree is controlled by constraints; therefore, you can tell the placer which cells are allowed in clock trees.
The skew is the time difference between the arrival time of clock edge to different cells. So narfnarf's explanation is not very proper on this matter.
The direct factor which controls the accuracy of duty cycle (here I assume 50% as non-50% is totally another story) is clock jitter.
Jitter defines the maximal period difference during the whole running time at any places.
A very small jitter means the transition times of clock cells are extremely balanced, normally in the cost of larger clock tree with extra area and power overhead.
Ouch!
OK, I am not an expert on analogue but I try to explain.
Yes, the transition time of cell depends on input transition time and output load. Assuming the input transition time is Ti and output load is Lo, the transition time of a cell is
T(up)=G(up)*Ti(up)*Lo and T(down)=G(down)*Ti(down)*Lo (we have used two assumptions here, 1. the equation is simplified into linear 2. up input caused a positive output)
The G here depends on the cell structure, in detail, is the density of P and N doping and the area of the doping region. The G itself means the amplify factor of input voltage to output current.
Unfortunately, the G for P Mos and N mos are different so normal CMOS transistors have different open and shut down time, which is the source of different up and down transition time.
By carefully compensation and match of the amplification factor, G, the balanced CMOS cell have similar G for PMOS and NMOS. Therefore, in most conditions, G(up) == G(down).
Supposing all cells in a clock tree have G(up) == G(down), a direct consequence will be Ti(up) == Ti(down). And finally T(up) == T(down).
In other words, although transition time depends on input transition and output load, as long as the G of PMOS and NMOS is equal, the positive edge transition and negedge transition will be the same. The transition time of a cell is not a fixed value but T(up) == T(down) in a balanced cell.
each clock buf/inv will have a same rise and fall