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If there is no documentation on PDK,
The simple way to choose better capacitor- is to perform parasitic extraction by Calibre/Assura end check extracted netlist for parasitic capacitance.
The obvious answer is for there to be no bulk (SOI on
high resistivity handle). But that fails the penny-per-die
test.
Some RF flows put the MIM cap, or one of them, up high in
the interconnect stack to minimize bottom plate parasitic
capacitance.
If you want zero just for the cap in isolation, you have few
choices. If you want zero parasitics including fringing to
adjacent X/Y/Z interconnect, that becomes none. Then
you have to account for and deal with it.
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