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Help with coding explaination

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jianhuachews

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Hi guys can any tell me what does this means?!?

Code: 
if(rst='1') then
            temp <= (0=> '0', others => '1');

from my understanding, it's supposed to be, bit 0 = '0' when rst = '1', right?

i have a ring counter that uses this code but i don't have to hit on a reset button(when pressed = '1') on my board to make the ring counter start. why is it so?
 

ring counter should start counting without resetting

sygnal temp : std_logic_vector(0 to 7); or (7 downto 0)
 

yes. but the thing is i dont understand why.. that means if i don't press on reset, by default, the data is 0000, am i right? i downloaded my program to the board but ringcounter starts without me having to press on reset( which is actually the correct behavior), but i don't understand why does it work when my code goes if rst='1' then bit 0 = '0', and all others goes to '1'
 

because to understand the operation of the counter need to know how work the electronic circuit, and insufficiently know as described this counter in vhdl

simulator is not working properly. More precisely, he does not have the initial conditions and begins to count only after they are given by reset/
 
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On a real circuit, values can only be '1' or '0'. In VHDL, they will default to 'UUU' (uninitialised). Any good synthesisor should take the power up value from the asynchronous reset state, so on your FPGA the counter should start from "100000.." when it powers on. If you never reset it, and it is always counting, it will overflow back to "00000".

You have only posted a small snippet of your code. Reset conditions are perfectly normal in VHDL, and there is usually no need to reset logic in hardware. Its usually best to asert the async reset at the start of a testbench.
 

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