Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PLL- Not locking due to charge pump

Status
Not open for further replies.

Ayyanar M

Junior Member level 1
Joined
Aug 2, 2011
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,393
Hi,

Am having 1mV oscillation in VCO control voltage at locking time........ Because of this my vco output frequency is varying........ here i used charge pump current s 10uA.......


LPF components are:R=10Kohm ,C1=150pF,c2=15pF........



Can anyone give me a suggestion to lock this??
 

Attachments

  • phase_noise.png
    phase_noise.png
    9.7 KB · Views: 129

Is it oscillation (a loop stability problem) or is it just charge pump ripple?
1mV seems like you could pick up that noise almost anywhere.
 
Hi,
This is because you chosed a high bandwidth for your PLL.
Try to reduce it and select also a good phase margin.
This will certainly solve your problem.
 

thanks to all...

Can anyone tell me how to calculate the total loop bandwidth of PLL in cadence?

And also phase margin?

What should be the range for these two for (upto 500MHz)?

Pls reply soon................
 

hi dick_freebird,

1mV oscillation is my LPF output that is VCO input... sorry dont consider the above phase noise plot.

see the attached waveform... there i found loop bandwidth and phase margin of the loop.........

Pls see it and reply me soon,,,,,,see the control voltage waveform too.....volt_control.png

loop_bandwidth.png
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top