Please suggest the way to understand new IP

Hello Friends,

I'm new in this field. I'm having difficulties to understand the verification of I2C IP (consists the verilog code and testbenches in both master and slave mode). Could anyone suggest what is the right way to understand the new IP and verification process? what are the checks should I run to verify both master and slave mode.

1) Create the theorethical models for the I2C master and slave in verilog. Abstract youself as much as possible from logic issues (how was implemented?) and concentrate on functional behaviour (how it works?) when designing the models. Avoid using logic in your models.


2) Use the models in the simulations to test if the IP behaviour matches the models. Ideally, if you connect them this way:

Master I2C IP <--> Slave I2C Model If they work together, then it's ok!
Master I2C Model <--> Slave I2C IP If they work together, then it's ok!
Master I2C IP <--> Slave I2C IP If they work together, then it's ok!

If they pass these 3 tests than you can consider your IPs properly verified.

Don't change the models when the test fails just to make them pass. Always check what has failed. Your models can be wrong, but double check, before changing anything.

Thanks fcfusion! I'm working on that.

I have one more question about testing speed , as I2C comes with different modes (e.g. standard, fast, high-speed), could you please suggest the way to verify it.

I believe the differences between these modes are only at the physical (electrical) level. In terms of code there are no differences so your models can be used to verify any of these modes.

Is it possible to change the clock frequency or increase it based on some clock multiplier in the TB-model for different modes of operation ?

Yes of course. Create all the clock sources with the frequencies you need. Then use a multiplexer to choose which one is used for your components.