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    [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    dear sir:

    recently i design a switched-capacitor circuit in tsmc 0.18um, in the circuit a CMOS transmission gate connect to PAD and an OPAMP input (high impedence), the switch size is << ESD protection mos in PAD, do the small swith need
    obey ESD rule? for example, enlarge contact to poly distance ...
    thank you very much!!


    sethtalk

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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Yes. I think it needs drain contact space.


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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    but if the small swith pass some ESD current, it represent the high impedance node (it connect to op input)
    have leakage path, ie some device is die??



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Yes. Small device will be easy to be damaged in ESD event. If possible, a resistor can be series connected to limit ESD current.



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    If you have already analog IO with a ESD protection before internal switch then nothing needed else,- IO incorporates all necessary structures to bypass a discharge current through themself. If switch is connected to pure bond pad directly, then you have to follow a fab ESD design guidelines.


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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Quote Originally Posted by leo_o2 View Post
    Yes. Small device will be easy to be damaged in ESD event. If possible, a resistor can be series connected to limit ESD current.
    leo_o2:
    i forget to say that i can't use a series resistor connect to the switch,it will degrade analog performance,



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    You will need ESD protection on the input since right now you do not have safe path to VDD/GND for ESD pulse. You should add RPO (silicide block) layer on the drain side of your MOS but it will slightly increase its resistance so might degrade the perfromance.
    In your case might be the safest way to add some schotky diodes to gnd and vdd . But agin it adds capacitance....



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Quote Originally Posted by sethtalk View Post
    dear sir:

    recently i design a switched-capacitor circuit in tsmc 0.18um, in the circuit a CMOS transmission gate connect to PAD and an OPAMP input (high impedence), the switch size is << ESD protection mos in PAD, do the small swith need
    obey ESD rule? for example, enlarge contact to poly distance ...
    thank you very much!!


    sethtalk
    connecting an I/O pad to a MOSFET gate requires CDM protection in deep-submiron processes, which is usually implemented as a small resistor (50-200 Ohm) followed on the gate side by HBM diode protection (e.g. reverse diodes to power/ground)

    your input CMOS switch is already implementing a small version of this CDM protection by adding channel resistance and diode to supplies through the S/D to body junction diodes, they will be small by ESD standards by it is a lot more protection than having nothing at all

    You have to balance the analog performance with the yield problems ensuing from ESD sensitivity, this depends on the target application (market or research) and your specs



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Every source or drain connected to a pad should follow ESD rules.



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Quote Originally Posted by dick_freebird View Post
    Every source or drain connected to a pad should follow ESD rules.
    S/D need only HBM protection which he already has according to his opening post, his concern was the gate terminal coming after the CMOS switch...



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    Re: [ESD question]do a cmos swith which connected to PAD should obey ESD rule?

    Quote Originally Posted by sethtalk View Post
    dear sir:

    recently i design a switched-capacitor circuit in tsmc 0.18um, in the circuit a CMOS transmission gate connect to PAD and an OPAMP input (high impedence), the switch size is << ESD protection mos in PAD, do the small swith need
    obey ESD rule? for example, enlarge contact to poly distance ...
    thank you very much!!


    sethtalk
    may not obey the ESD rule. Yet the ESD structre is supposed to be rail-based. for example, the 2 diodes are used in analogy pad. what's impoart, the ESD clamp used between power and gnd is supposed to work on normal state during ESD.
    And lots of such clamps are supposed to be used.



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