chip-monk
Newbie level 5
Following is a segment of a Verilog code I'm trying to synthesize.
adder_ks16 ks16_2(c_out, ,notoutAcc,SADmin,1'b0);
always @(posedge c_out or posedge signal_m)
begin
if(signal_m == 1)
SADmin <= 16'b1111_1111_1111_1111;
else
//#1 SADmin <= regAcc;
SADmin <= regAcc;
end
Module definition for adder_ks16 (16 Bit adder):
module adder_ks16(c_out,sum,A,B,c_in);
which basically implements the function: {c_out,sum} = A + B + c_in
When I try to synthesize this code using Cadence RTL Compiler, it gives the following error:
Warning : A combinational loop has been found. [TIM-20]
: The design 'ks_sa1' contains the following combinational loop:
ks16_2/c_out
SADmin_reg[14]/clk
SADmin_reg[14]/q
ks16_2/B[14]
ks16_2/B[14]
ks16_2/and_84/in_1
ks16_2/and_84/z
ks16_2/and_93/in_1
ks16_2/and_93/z
ks16_2/g1/in_1
ks16_2/g1/z
ks16_2/g2/in_3
ks16_2/g2/z
ks16_2/c_out
ks16_2/c_out
The combinational loop has been disabled.
Info : Deleting instances not driving any primary outputs. [GLO-32]
: Deleting 18 hierarchical instances.
: Optimizations like for example constant propagation or redundancy removal could change the connections so an instance does not drive any primary outputs anymore. To see the list of deleted instances, set the 'information_level' attribute to 2 or above.
Synthesis succeeded.
-------------------------------------------------
Functionally this design works, is there a command to set some attribute in cadence that could allow me to synthesize this code?
Are there any suggestions one might have for modification to this code? Even though the compiler says its a combinational loop, there is a sequential element (flip flop) involved.
Also does anyone have the manual 'Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler'? In case yes, please reply attaching the manual here.
Thanks.
adder_ks16 ks16_2(c_out, ,notoutAcc,SADmin,1'b0);
always @(posedge c_out or posedge signal_m)
begin
if(signal_m == 1)
SADmin <= 16'b1111_1111_1111_1111;
else
//#1 SADmin <= regAcc;
SADmin <= regAcc;
end
Module definition for adder_ks16 (16 Bit adder):
module adder_ks16(c_out,sum,A,B,c_in);
which basically implements the function: {c_out,sum} = A + B + c_in
When I try to synthesize this code using Cadence RTL Compiler, it gives the following error:
Warning : A combinational loop has been found. [TIM-20]
: The design 'ks_sa1' contains the following combinational loop:
ks16_2/c_out
SADmin_reg[14]/clk
SADmin_reg[14]/q
ks16_2/B[14]
ks16_2/B[14]
ks16_2/and_84/in_1
ks16_2/and_84/z
ks16_2/and_93/in_1
ks16_2/and_93/z
ks16_2/g1/in_1
ks16_2/g1/z
ks16_2/g2/in_3
ks16_2/g2/z
ks16_2/c_out
ks16_2/c_out
The combinational loop has been disabled.
Info : Deleting instances not driving any primary outputs. [GLO-32]
: Deleting 18 hierarchical instances.
: Optimizations like for example constant propagation or redundancy removal could change the connections so an instance does not drive any primary outputs anymore. To see the list of deleted instances, set the 'information_level' attribute to 2 or above.
Synthesis succeeded.
-------------------------------------------------
Functionally this design works, is there a command to set some attribute in cadence that could allow me to synthesize this code?
Are there any suggestions one might have for modification to this code? Even though the compiler says its a combinational loop, there is a sequential element (flip flop) involved.
Also does anyone have the manual 'Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler'? In case yes, please reply attaching the manual here.
Thanks.
Last edited: